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TMS320F28P550SJ: ADC timing specs between data sheet and user manual

Frank Zhang
Prodigy 70 points
Part Number: TMS320F28P550SJ

Tool/software:

Hi,

According to the data sheet ('Data sheet F28P55x'), it says the conversion time for each sample can be 180ns.

But if you look at the ADC specs from the user manual, I believe for F28P550SJ (150MHz sys clock rate), the ADC peripheral clock can only go as fast as 75MHz. That means we need to set Prescale = 2, which leads to the conversion time way longer than 180ns.

Can you please explain to me why 180ns conversion time was used in the Data Sheet?

Thank you,

Frank

  • 0
    TI__Intellectual 2990 points

    Hi Frank,

    ADC Conversion time is tsh(sample and hold time) + tlat .

    let me know if this answered your question.

    Thanks,

    Susmitha

  • 0 in reply to Susmitha Bumadi
    Prodigy 70 points

    Hi Susmitha,

    Thank you for your reply, but it didn't answer my question. 

    I understand the ADC conversion time is tsh + tlat. Let's use 1 clock cycle for tsh which is very extreme, and as mentioned the minimum number for Prescale is 2 which gives peripheral clock at 75Mhz and the associated tlat is 35 peripheral clock cycle.

    So the total clock cycle for ADC conversion is tsh + tlat = 1 + 35 = 36. 

    Given the clock rate is 75MHz, each clock cycle is 13,3ns, the total ADC conversion time is 36 * 13.3ns = 478.8ns. This is way larger than the 180ns stated in the Data sheet. 

    So my question is how is 180ns derived? and What did I miss in my calculation?

    Thank you,

    Frank

  • 0 in reply to Frank Zhang
    TI__Intellectual 2990 points

    Hi Frank,

    Given the max ADC clock rate is 75MHz, each clock cycle is 13.3ns

    ADC conversion time = 14 x 13.33 ns = 186.62 ns

    Thanks,
    Susmitha

  • 0 in reply to Susmitha Bumadi
    Prodigy 70 points

    Hi Susmitha,

    It is much clearer now. But I do have another question. You mentioned that ADC conversion time is tsh + tlat, does tsh vary with different sampling window the user decides to use? If yes, does the 186ns assume minimum sampling window?

    Thanks,

    Frank

  • +1 in reply to Frank Zhang
    TI__Intellectual 2990 points

    Hi Frank,

    Thats right...Sampling and hold time can be set by user accordingly.

    FYI, the sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.

    Thanks,

    Susmitha

  • 0 in reply to Susmitha Bumadi
    Prodigy 70 points

    Thank you for your reply.