TMS320F28P550SJ: ADC timing specs between data sheet and user manual

Hi Frank,

ADC Conversion time is tsh(sample and hold time) + tlat .

let me know if this answered your question.

Thanks,

Susmitha

Hi Susmitha,

Thank you for your reply, but it didn't answer my question. 

I understand the ADC conversion time is tsh + tlat. Let's use 1 clock cycle for tsh which is very extreme, and as mentioned the minimum number for Prescale is 2 which gives peripheral clock at 75Mhz and the associated tlat is 35 peripheral clock cycle.

So the total clock cycle for ADC conversion is tsh + tlat = 1 + 35 = 36. 

Given the clock rate is 75MHz, each clock cycle is 13,3ns, the total ADC conversion time is 36 * 13.3ns = 478.8ns. This is way larger than the 180ns stated in the Data sheet. 

So my question is how is 180ns derived? and What did I miss in my calculation?

Thank you,

Frank

Hi Frank,

Given the max ADC clock rate is 75MHz, each clock cycle is 13.3ns

ADC conversion time = 14 x 13.33 ns = 186.62 ns

Thanks,
Susmitha

Hi Susmitha,

It is much clearer now. But I do have another question. You mentioned that ADC conversion time is tsh + tlat, does tsh vary with different sampling window the user decides to use? If yes, does the 186ns assume minimum sampling window?

Thanks,

Frank

Thank you for your reply.