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Original question:

TMS320F28P650DK: The Flash / RAM questions of F28P65x dual-core devices.

TMS320F28388D: RAM questions of dual-core application.

Yen Ting Liu
Prodigy 40 points
Part Number: TMS320F28388D
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello, I am currently using the F28388 chip for dual-core applications. Below is a snippet of the .cmd file for CPU2:

RAMM0M1       : origin = 0x000002, length = 0x0007F6     /* on-chip RAM block M1 */
RAMM1_RSVD    : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD0D1       : origin = 0x00C000, length = 0x001000
// This section is set to owned by CPU1 for data
CPU1RAMGS0GS6   : origin = 0x00D000, length = 0x007000
// This section is set to owned by CPU1 for Ramfunc
CPU1RAMGS7GS9   : origin = 0x014000, length = 0x003000
// This section is set to owned by CPU2 for data
CPU2RAMGS10GS12  : origin = 0x017000, length = 0x003000
// This section is set to owned by CPU2 for Ramfunc
CPU2RAMGS13GS15  : origin = 0x01A000, length = 0x003000
 
If the memory block RAMD0D1 is immediately followed by CPU1RAMGS0GS6, which is allocated for CPU1's data, should the last 8 x 16 words of CPU2's RAMD0D1 block be reserved to avoid prefetching into an invalid memory area?

Follow-up question: Based on the .cmd file above, what would happen if CPU2 prefetches into a memory region owned by CPU1? Are there any registers where this behavior can be observed?

Currently, we are encountering an issue where, when executing a function located at the very end of RAMD0D1 (occupying the last 8 words), there is a chance of jumping into illegal_isr(), but this does not always occur. We would like to confirm whether this behavior is caused by prefetching into an invalid memory region.

  • 0
    TI__Expert 8231 points

    Hi Yen,

    Can you share the complete linker cmd file for further analysis (both cpu1 and cpu2).

    Have you tried using the linker cmd tool in sysconfig to configure the memory regions, please have a look at them also.

    Please take a look at dual core linker cmd threads - (+) TMS320F28388D: TMS320F28388D - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums

    Thanks

    Aswin

  • +1 in reply to Aswin P
    Prodigy 40 points

    Hi Aswin,

    I believe I've found the solution. In the TMS320F2838x Real-Time MCUs Silicon Errata document, it is mentioned that prefetching to the end of a legal memory region and crossing into an illegal memory region can cause errors.


    From our experimental results, when entering the ILLIGAL_ISR, the AccessProtectionRegs.NMAVFLG.CPUFETCH flag on CPU2 is indeed raised, and the NMCPUFAVADDR indicates the illegal access address as 0xD000. (CPU1RAMGS0GS6 start from 0xD000 is configured only be access by CPU1, it is invalid for CPU2)


    By modifying the .cmd file to avoid using the last 8 words of RAM D1, the issue no longer occurs.

    Thanks

    Yen