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RE: TMS320F28377S: spi and dma receive stuck

Joe Ji
Expert 3910 points


Hi Delaney

My customer also come across this issue, we have discussed in the E2E thread before: link.

the SPIA is allocated to CPU2, and SPI internal loopback is tested to show the DMA setting is correct.

But when disable the internal loopback and communicate with SPI slave device, the data address has wrong offset as shown below, the first word 0x0001 should located in [0], but now it located in [16]:

the target word quantity is 80 words, SPI works in 10M.

I find the root cause of this wrong data address offset is that SPI overflow, when RXFFOVF is set, the data address offset is 16 words, but when RXFFOVF is not set, the data address offset is 0 word, which is correct.

I do the below check:

1. initialize DMA first and standby before SPI master enable data transmission. issue is not fixed.

2. Try to reset the SPI manually when DSP run --- there is no more RXFFOVF and data address is correct.

I doubt that DMA is not ready when the first RXFFIL is generated which cause RXFFOVF.

 

Thanks

Joe

  • 0
    TI__Mastermind 20025 points

    Hi Joe,

    I have moved this response to a new thread so I am able to tell the issues apart.

    If the SPISTS.OVERRUN_FLAG is being set, new data is being sent by the slave device before the DMA has completed the transfer of the previous data. Instead of clearing the flag in software, I would suggest resolving the larger issue of why this is happening so there is no data lost. A couple questions:

    1. Just to verify - Is the DMA_SPIARX trigger still being used to trigger the DMA CH6 transfer? And the burst size of the DMA channel still matches the SPI RX FIFO level set?
    2. Do you have other DMA channels enabled for CPU 2 DMA? If so, which channel priority scheme is being used (round robin or CH1 priority)? DMA CH6 could be getting blocked waiting for other channels to finish their transfers, and therefore not transferring over the data in time.
    3. What SPI baud rate is being used? What is the format of the data being sent back by the slave device (are there more than 16 words being sent one after another)?

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Expert 3910 points
    Delaney Woodward said:
    Just to verify - Is the DMA_SPIARX trigger still being used to trigger the DMA CH6 transfer? And the burst size of the DMA channel still matches the SPI RX FIFO level set?

    Yes, the DMA and SPI cooperation is also verified when the code runs SPI only, the function is correct without overflow.

    Delaney Woodward said:
    Do you have other DMA channels enabled for CPU 2 DMA? If so, which channel priority scheme is being used (round robin or CH1 priority)? DMA CH6 could be getting blocked waiting for other channels to finish their transfers, and therefore not transferring over the data in time.

    there is another DMA5 for SPI TX, I think that might be the point, since SPI is full duplex if TX DMA has priority and send/ receive at the same time, it may cause RX overflow. So i will let customer to use DMA1 for SPI RX and enable CH1 priority mode to see whether the over flow issue can be solved.

    Delaney Woodward said:
    What SPI baud rate is being used? What is the format of the data being sent back by the slave device (are there more than 16 words being sent one after another)?

    Baud rate is 10Mhz, there are 80 words sent one after another in one data package.

    Thanks

    Joe

  • 0 in reply to Delaney Woodward
    TI__Expert 3910 points

    Hi Delaney

    The SPI+DMA Rx problem is still unresolved. 

    I used 28377D  CPU2  for comunication，spia and dma1 to read 44 words from Master(28377D) and trigger a DMA interrupt. 

    SPI Baud rate is 10Mhz, there are 44 words sent one after another in one data package.  200us send each other 。The following code is the configuration of 28377D  ：

     slave SPI  initialization code is as follows :

    //DSP1 To DSP 2
void InitSpia(void)
{

//Initial SPIC FIFO Length
SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
SpiaRegs.SPICCR.bit.SPICHAR = 15;

SpiaRegs.SPICCR.bit.HS_MODE = 0;        //High Speed Mod SPIClK = 200M
SpiaRegs.SPICCR.bit.SPILBK = 0;

// SPI interrupts are disabled
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 0;   //SPI Running in slave Mode

SpiaRegs.SPICTL.bit.TALK = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;

//SpiaRegs.SPICTL.bit.SPIINTENA = 0;
SpiaRegs.SPICTL.bit.SPIINTENA = 1;

// Set the baud rate
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 4;   // Hmode = 0 50M/5= 10M

// Set FREE bit
// Halting on a breakpoint will not halt the SPI
SpiaRegs.SPIPRI.bit.FREE = 1;

// Release the SPI from reset
SpiaRegs.SPICCR.bit.SPISWRESET = 1;

}
     

    Master SPI configuration :

    void InitSpia(void)
{

//Initial SPIC FIFO Length
SpiaRegs.SPICCR.bit.SPISWRESET = 0;
SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
SpiaRegs.SPICCR.bit.SPICHAR = 15;

SpiaRegs.SPICCR.bit.HS_MODE = 0;                      //High Speed Mod SPIClK = 200M
SpiaRegs.SPICCR.bit.SPILBK = 0;

// SPI interrupts are disabled
SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; //SPI Running in slave Mode

SpiaRegs.SPICTL.bit.TALK = 1;
SpiaRegs.SPICTL.bit.CLK_PHASE = 0;

//SpiaRegs.SPICTL.bit.SPIINTENA = 0;
SpiaRegs.SPICTL.bit.SPIINTENA = 1;

// Set the baud rate
SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 4;  // Hmode = 0 50M/5 = 10M

// Set FREE bit
// Halting on a breakpoint will not halt the SPI
SpiaRegs.SPIPRI.bit.FREE = 1;
// Release the SPI from reset
SpiaRegs.SPICCR.bit.SPISWRESET = 1;
}

    Both salve and master FiFO  level is set to  8。

    slave using DMA CH1 to RX 。Master Using DMA CH5 to TX

    slave DMA initialization code

    {

DMACH1AddrConfig(DMADest,&SpiaRegs.SPIRXBUF);
DMACH1BurstConfig(0,0,1);
DMACH1TransferConfig(43,0,1);
DMACH1WrapConfig(0,0,43,0);

DMACH1ModeConfig(DMA_SPIARX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
CHINT_END,CHINT_ENABLE);

}

    master DMA configure:

    {

DMACH5AddrConfig(&SpiaRegs.SPITXBUF,DMASource);
DMACH5BurstConfig(0,1,0);// Burst size, src step, dest step
DMACH5TransferConfig(43,1,0);// transfer size, src step, dest step
DMACH5WrapConfig(43,0,0,0);

DMACH5ModeConfig(DMA_SPIATX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
CHINT_END,CHINT_ENABLE);

}

    When Master send  data (0x01 0xFC  .....  CRC)，The RX result  as follows:

    We could found that the first words  will   be placed on the sixteenth words.

    when BurstConfig number is more than 1 words, the first words position is random.  such as follows :

    some times we found that  the raw data is not transfer completed.   

    Master  send data:

    9884 8884 7884 6884 5884 3884 2884 1884  884    10117 9117 8117 7117 6117 5117 3117 2117 1117  9884 8884 7884 6884 5884 3884 2884 1884  884    10117 9117 8117 7117 6117 5117 3117 2117 1117

    Slave recive data :

    9884 8884 7884 6884 5884 3884 2884 1884  884    10117 9117 8117 7117 6117 5117 3117 2117 1117  9883 8883 7883 6883 5883 3883 2883 1883  883    10116 9116 8116 7116 6116 5116 3116 2116 1116

    "9883 8883 7883 6883 5883 3883 2883 1883  883    10116 9116 8116 7116 6116 5116 3116 2116 1116 " is the data received in the previous frame

    the RX data as follow:

     

    In most cases, I found that  SPI RXFFOVF  has been set to 1. 

     I do the below check:

    the  spi register  is:

    Is there any error in the above dma & spi configuration ? 

  • 0 in reply to Joe Ji
    TI__Mastermind 20025 points

    Hi Joe,

    After looking at the configurations, here is what would likely be the issue:

    The DMA burst size being configured for both channels is 1, is that correct? If so, you want to configure the SPI FIFOs to trigger for every 1 word to correctly synchronize the SPI and the DMA (on both channels/devices). The below should be the SPI configurations to use:


    SpiaRegs.SPIFFRX.bit.RXFFIL = 0x1; // Set RX FIFO level (1 or more words present -> 1 word can be read by DMA)

    SpiaRegs.SPIFFTX.bit.TXFFIL = 0xF; // Set TX FIFO level (15 words or fewer present -> 1 word can be written by DMA)

    Let me know if this fixes the issue. You could also change the burst size to 8 instead, but this wouldn't work for sending 44 words since 44/8 doesn't divide evenly. 

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 50 points

    Hi Delaney.

    I'm the one who raised this question. 

    I tested it according to the suggestions you gave, but the problem still persists.

    I've read this article.

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1442843/tms320f28377s-spi-and-dma-receive-stuck

    In DMA Rx Interrupt Function .I restart the DMA Channel.

    //
// local_D_INTCH6_ISR - DMA Channel 6 ISR receive
//
__interrupt void local_D_INTCH6_RX_ISR(void)
{

    EALLOW;                                         // NEED TO EXECUTE EALLOW INSIDE ISR !!!
//    DmaRegs.CH1.CONTROL.bit.HALT = 1;
   
    DmaRegs.CH1.CONTROL.bit.RUN = 1;

    PieCtrlRegs.PIEACK.all = PIEACK_GROUP7;         // ACK to receive more interrupts
                                                    // from this PIE group
    EDIS;
    GetSPIDMARecData();
}

    The SPI overflow problem on the slave side has been resolved. But using same method , the problem  the master side still exists.

    Do you have any other suggestions?

  • 0 in reply to neil lan
    TI__Expert 3910 points

    Hi Delaney

    Neil Lan is the engineer from my customer, he proposed this issue to me and continue to communicate with you. could you please kindly follow up the issue with this thread?

    Thanks

    Joe

  • 0 in reply to Joe Ji
    TI__Mastermind 20025 points

    Hi Neil and Joe,

    What issue are you seeing on the master side? Are there any error flags being set for the SPI module on the master side code? Is there some data missing that is supposed to be transmitted?

    Please explain the current issue and share the updated code if possible so I can look into it.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Expert 3910 points

    Hi Delaney

    the Master side configuration is:

    SPI configuration:

    void InitSpia(void)
    {

    //Initial SPIC FIFO Length
    SpiaRegs.SPICCR.bit.SPISWRESET = 0;
    SpiaRegs.SPICCR.bit.CLKPOLARITY = 0;
    SpiaRegs.SPICCR.bit.SPICHAR = 15;

    SpiaRegs.SPICCR.bit.HS_MODE = 0;                      //High Speed Mod SPIClK = 200M
    SpiaRegs.SPICCR.bit.SPILBK = 0;

    // SPI interrupts are disabled
    SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; //SPI Running in slave Mode

    SpiaRegs.SPICTL.bit.TALK = 1;
    SpiaRegs.SPICTL.bit.CLK_PHASE = 0;

    //SpiaRegs.SPICTL.bit.SPIINTENA = 0;
    SpiaRegs.SPICTL.bit.SPIINTENA = 1;

    // Set the baud rate
    SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = 4; // Hmode = 0 50M/5 = 10M

    // Set FREE bit
    // Halting on a breakpoint will not halt the SPI
    SpiaRegs.SPIPRI.bit.FREE = 1;
    // Release the SPI from reset
    SpiaRegs.SPICCR.bit.SPISWRESET = 1;
    }

    master DMA configure:

    {

    DMACH5AddrConfig(&SpiaRegs.SPITXBUF,DMASource);
    DMACH5BurstConfig(0,1,0);// Burst size, src step, dest step
    DMACH5TransferConfig(43,1,0);// transfer size, src step, dest step
    DMACH5WrapConfig(43,0,0,0);

    DMACH5ModeConfig(DMA_SPIATX,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,
    SYNC_DISABLE,SYNC_SRC,OVRFLOW_DISABLE,SIXTEEN_BIT,
    CHINT_END,CHINT_ENABLE);

    }

    the master RX issue is the same as slave RX issue and SPI register reports the overflow error:

    When Slave send  data (0x01 0xFC  .....  CRC)，The Master RX result  as follows:

    We could found that the first words  will  be placed on the sixteenth words.

    when BurstConfig number is more than 1 words, the first words position is random.  such as follows :

    some times we found that  the raw data is not transfer completed.   

    Slave send data:

    9884 8884 7884 6884 5884 3884 2884 1884  884    10117 9117 8117 7117 6117 5117 3117 2117 1117  9884 8884 7884 6884 5884 3884 2884 1884  884    10117 9117 8117 7117 6117 5117 3117 2117 1117

    Master receive data :

    9884 8884 7884 6884 5884 3884 2884 1884  884    10117 9117 8117 7117 6117 5117 3117 2117 1117  9883 8883 7883 6883 5883 3883 2883 1883  883    10116 9116 8116 7116 6116 5116 3116 2116 1116

    "9883 8883 7883 6883 5883 3883 2883 1883  883    10116 9116 8116 7116 6116 5116 3116 2116 1116 " is the data received in the previous frame

    the RX data as follow:

     

    In most cases, I found that  SPI RXFFOVF  has been set to 1. 

     I do the below check:

    the  spi register  is:

    Thanks

    Joe

  • 0 in reply to Joe Ji
    TI__Mastermind 20025 points

    Hi Joe,

    This looks to be the same problem I mentioned before. The SPI FIFO levels are set to 8 but the DMA burst size they are using is 1. These need to match in order for correct operation. The DMA burst size either needs to be changed to 8, or the SPI FIFO levels need to be changed to 1.

    Best Regards,

    Delaney