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TMS320F28379D: Synchronizing the EPWM1 with External Sync In

Part Number: TMS320F28379D

Tool/software:

Dear Experts,

I am trying to generate a PWM using PWM module while the counter is in synch with an external trigger. TO achieve this, I'm triggering a pulse on GPIO10 which is associated with INPUT5SELECT. Furthermore, I also initialized TBCTL's bit PHSEN as 1 to make CTR to ZERO when triggered externally.

Here is the snippet of the initialzations sections of the code.

void PWM0_Init(void)
{
          EALLOW;
          EPwm1Regs.TBCTL.bit.CTRMODE = 0;             // Count up
          EPwm1Regs.TBPRD = 10000;                    // Set timer period
          EPwm1Regs.TBCTL.bit.PHSEN = 1;               // Enable phase loading
          EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;          // Phase is 0
          EPwm1Regs.TBCTR = 0x0000;                    // Clear counter
          EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;           // Clock ratio to SYSCLKOUT
          EPwm1Regs.TBCTL.bit.CLKDIV = 0;
          EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;            // SYNC output on CTR = 0
          // Setup shadow register load on ZERO
          EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
          EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
          EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
          EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
          // Set Compare values
                // Set compare A value
          // Set actions
          EPwm1Regs.AQCTLA.bit.ZRO = 2;                // Set PWM1A on Zero
          EPwm1Regs.AQCTLA.bit.CAU = 1;                // Clear PWM1A on event A, up count

          //SOCA to ADC
          EPwm1Regs.ETSEL.bit.SOCAEN=1;
          EPwm1Regs.ETSEL.bit.SOCASEL=1;
          EPwm1Regs.ETPS.bit.SOCAPRD = 1;
          EPwm1Regs.ETCLR.bit.SOCA = 1;
          EDIS;
}

void X_bar(void)

{
    EALLOW;

    InputXbarRegs.INPUT5SELECT = 10;

    EDIS;

}

Despite of these initializations, I don't see any changes in PWM frequency while I keep altering the external trigger frequency.

THanks in advance.

Regards,

Rajesh,

  • Hi Allison,

    Thanks for the information. I referred to the above links and I did the exactly what Marlyn said. However, I dont see any change. 

    What bothers me is, pulse width is still being controlled without any pulse given to the EXTSYNCIN1. It is behaving as if PWM1 was initialized as master(not being driven by the external sync signal).

    Here is my complete code.

    #include "F28x_Project.h"
    
    extern void InitSysCtrl(void);
    extern void InitPieCtrl(void);
    extern void InitPieVectTable(void);
    
    interrupt void TimerOvf(void);
    interrupt void ADCs_EOC(void);
    
    void Initialize_GPIO(void);
    void Custom_Init(void);
    void timer0_init(void);
    void PWM0_Init(void);
    void Init_ADCs(void);
    void X_bar(void);
    
    int b=0;
    float a=0;
    
    
    void main(void)
    {
    
       InitSysCtrl();
       Custom_Init();
       PWM0_Init();
       Init_ADCs();
    
       DINT;
       Initialize_GPIO();
       InitPieCtrl();
    
       IER = 0x0000;
       IFR = 0x0000;
       InitPieCtrl();
       InitPieVectTable();
    
       EALLOW;
       PieCtrlRegs.PIEIER1.bit.INTx1 = 1;    //ADC-A1
       PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
       PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
    
    
       PieVectTable.TIMER0_INT = &TimerOvf;
       PieVectTable.ADCA1_INT = &ADCs_EOC;
       PieCtrlRegs.PIECTRL.bit.ENPIE= 1;
       EDIS;
    
       IER |= 3;
       EINT;  // Enable Global interrupt INTM
       ERTM;  // Enable Global realtime interrupt DBGM
       timer0_init();
       CpuTimer0Regs.TCR.bit.TSS=0;
       while(1)
           {
    
            }
    }
    void Initialize_GPIO(void)
    {
        EALLOW;
        GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;
        GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
        GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
        GpioCtrlRegs.GPCDIR.bit.GPIO73= 1;
        GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //EPwm1
        EDIS;
    
    }
    void Custom_Init(void)
    {
        EALLOW;
        ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1;
        ClkCfgRegs.AUXPLLMULT.bit.IMULT=20;
        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
        ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
        ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
        CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;   ///source initsysctrl
        CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
        CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
        CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
        DevCfgRegs.CPUSEL0.bit.EPWM1 = 0;
        EDIS;
    }
    
    
    void timer0_init(void)
    {
        EALLOW;
        CpuTimer0Regs.PRD.bit.MSW = 0x0004;
        CpuTimer0Regs.PRD.bit.LSW = 0x0080;
        CpuTimer0Regs.TPR.bit.TDDR = 0x0013;
    
    
        CpuTimer0Regs.TCR.bit.TIE= 1;
        CpuTimer0Regs.TCR.bit.TSS=1;
        CpuTimer0Regs.TCR.bit.FREE=0;
        CpuTimer0Regs.TCR.bit.TRB=0;
        EDIS;
    }
    void TimerOvf(void)
    {
        b= b+1;
    
        if(b>10)
        {
            b=1;
        }
        GpioDataRegs.GPBTOGGLE.bit.GPIO34=1;
        GpioDataRegs.GPATOGGLE.bit.GPIO31=1;
        CpuTimer0Regs.TCR.bit.TIF = 1;
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }
    
    void ADCs_EOC(void)
    {
    
        a = AdcaResultRegs.ADCRESULT0; //Va
        EPwm1Regs.CMPA.bit.CMPA = 10000*a/4095;
    
    
        AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }
    
    void X_bar(void)
    
    {
        EALLOW;
    
        InputXbarRegs.INPUT5SELECT = 10;
    
        GpioDataRegs.GPASET.bit.GPIO10 = 1;
        GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
    
        EDIS;
    
    }
    
    void PWM0_Init(void)
    {
              EALLOW;
              EPwm1Regs.TBCTL.bit.CTRMODE = 0;             // Count up
              EPwm1Regs.TBPRD = 10000;                    // Set timer period
              EPwm1Regs.TBCTL.bit.PHSEN = 1;               // Enable phase loading
              EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;          // Phase is 0
              EPwm1Regs.TBCTR = 0x0000;                    // Clear counter
              EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;           // Clock ratio to SYSCLKOUT
              EPwm1Regs.TBCTL.bit.CLKDIV = 0;
              EPwm1Regs.TBCTL.bit.SYNCOSEL = 1;            // SYNC output on CTR = 0
              // Setup shadow register load on ZERO
              EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
              EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
              EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
              EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
              // Set Compare values
                    // Set compare A value
              // Set actions
              EPwm1Regs.AQCTLA.bit.ZRO = 2;                // Set PWM1A on Zero
              EPwm1Regs.AQCTLA.bit.CAU = 1;                // Clear PWM1A on event A, up count
    
              //SOCA to ADC
              EPwm1Regs.ETSEL.bit.SOCAEN=1;
              EPwm1Regs.ETSEL.bit.SOCASEL=1;
              EPwm1Regs.ETPS.bit.SOCAPRD = 1;
              EPwm1Regs.ETCLR.bit.SOCA = 1;
              EDIS;
    }
    
    void Init_ADCs(void)
    {
        EALLOW;
                AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
                AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
                AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
    
                AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
                AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
                AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    
                AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                DELAY_US(1000);
    
                AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
                AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
                AdccRegs.ADCCTL2.bit.PRESCALE = 6;
    
                AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin A0
                AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;  //SOC1 will convert pin A1
                AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin A2
                AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC3 will convert pin A3
                AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;  //SOC4 will convert pin A4
                AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;  //SOC5 will convert pin A5
    
                AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin B2
                AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin B3
                AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4;  //SOC2 will convert pin B4
                AdcbRegs.ADCSOC3CTL.bit.CHSEL = 5;  //SOC3 will convert pin B5
    
                AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin C2
                AdccRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin C3
                AdccRegs.ADCSOC2CTL.bit.CHSEL = 4;  //SOC2 will convert pin C4
                AdccRegs.ADCSOC3CTL.bit.CHSEL = 5;  //SOC3 will convert pin C5
    
    
                AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
                AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
                AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
    
                AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
                AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
                AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    
        EDIS;
    }
    

    Thanks in advance.

    Regards,

    Rajesh.

  • Hi Rajesh,

    Did you take a look at the other links as well? I believe the last one has a project example featuring external sync setup with GPIO32.

    I have a few more suggestions on how to help debug this:

    • You can also set the SYNC-OUT SELECT for EPWM1 to be "SYNC-IN", meaning EPWM's sync-out pulse will reflect when it receives a sync pulse from the external source. From here, you can use OUTPUT XBAR MUX 14 to output the sync pulse on a GPIO to scope (OUTPUTXBAR MUX 14 you can select EXTSYNCOUT). If you look at the SYNCOUT pulse, you can check that the pulse is seen when you change the state of your external signal.
    • Another tip would be stepping through the code line by line and double checking the PWM registers and GPIO/external sync related registers are changing as expected. Do you see them reflect the values expected? 

    Best Regards,

    Allison

  • Hi Allison,

    I tried reading the GPIO10 using GPDAT registers. Its being read, however, the PWM1 is being regulated by the CMPA. Here is the code:

    #include "F28x_Project.h"
    
    extern void InitSysCtrl(void);
    extern void InitPieCtrl(void);
    extern void InitPieVectTable(void);
    
    interrupt void TimerOvf(void);
    interrupt void ADCs_EOC(void);
    
    void Initialize_GPIO(void);
    void Custom_Init(void);
    void timer0_init(void);
    void PWM1_Init(void);
    void Init_ADCs(void);
    void X_bar(void);
    
    int b=0;
    float a=0;
    
    
    void main(void)
    {
    
       InitSysCtrl();
       Custom_Init();
       PWM1_Init();
       Init_ADCs();
    
       DINT;
       Initialize_GPIO();
       InitPieCtrl();
    
       IER = 0x0000;
       IFR = 0x0000;
       InitPieCtrl();
       InitPieVectTable();
    
       EALLOW;
       PieCtrlRegs.PIEIER1.bit.INTx1 = 1;    //ADC-A1
       PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
       PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
    
    
       PieVectTable.TIMER0_INT = &TimerOvf;
       PieVectTable.ADCA1_INT = &ADCs_EOC;
       PieCtrlRegs.PIECTRL.bit.ENPIE= 1;
       EDIS;
    
       IER |= 3;
       EINT;  // Enable Global interrupt INTM
       ERTM;  // Enable Global realtime interrupt DBGM
       timer0_init();
       CpuTimer0Regs.TCR.bit.TSS=0;
       while(1)
           {
    
            }
    }
    void Initialize_GPIO(void)
    {
        EALLOW;
        GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;
        GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
        GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
        GpioCtrlRegs.GPCDIR.bit.GPIO73= 1;
        GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //EPwm1
        EDIS;
    
    }
    void Custom_Init(void)
    {
        EALLOW;
        ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1;
        ClkCfgRegs.AUXPLLMULT.bit.IMULT=20;
        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
        ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
        ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
        CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;   ///source initsysctrl
        CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
        CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
        CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
        DevCfgRegs.CPUSEL0.bit.EPWM1 = 0;
        EDIS;
    }
    
    
    void timer0_init(void)
    {
        EALLOW;
        CpuTimer0Regs.PRD.bit.MSW = 0x0004;
        CpuTimer0Regs.PRD.bit.LSW = 0x0080;
        CpuTimer0Regs.TPR.bit.TDDR = 0x0013;
    
    
        CpuTimer0Regs.TCR.bit.TIE= 1;
        CpuTimer0Regs.TCR.bit.TSS=1;
        CpuTimer0Regs.TCR.bit.FREE=0;
        CpuTimer0Regs.TCR.bit.TRB=0;
        EDIS;
    }
    void TimerOvf(void)
    {
        b= b+1;
    
        if(b>10)
        {
            b=1;
        }
        if(GpioDataRegs.GPADAT.bit.GPIO10==1)
        {GpioDataRegs.GPBTOGGLE.bit.GPIO34=1;
        GpioDataRegs.GPATOGGLE.bit.GPIO31=1;
        }
        CpuTimer0Regs.TCR.bit.TIF = 1;
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }
    
    void ADCs_EOC(void)
    {
    
        a = AdcaResultRegs.ADCRESULT0; //Va
        EPwm1Regs.CMPA.bit.CMPA = 10000*a/4095;
    
    
        AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }
    
    void X_bar(void)
    
    {
        EALLOW;
    
        InputXbarRegs.INPUT5SELECT = 10;
    
      //  GpioDataRegs.GPASET.bit.GPIO10 = 1;
     //   GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
    
        EDIS;
    
    }
    
    void PWM1_Init(void)
    {
              EALLOW;
    
              EPwm1Regs.TBCTL.bit.CTRMODE = 0;             // Count up
              EPwm1Regs.TBPRD = 10000;                    // Set timer period
              EPwm1Regs.TBCTL.bit.PHSEN = 1;               // Enable phase loading
              EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;          // Phase is 0
              EPwm1Regs.TBCTR = 0x0000;                    // Clear counter
              EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;           // Clock ratio to SYSCLKOUT
              EPwm1Regs.TBCTL.bit.CLKDIV = 0;
              EPwm1Regs.TBCTL.bit.SYNCOSEL = 0;            // SYNC output on CTR = 0
              // Setup shadow register load on ZERO
              EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
              EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
              EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
              EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
              // Set Compare values
                    // Set compare A value
              // Set actions
              EPwm1Regs.AQCTLA.bit.ZRO = 2;                // Set PWM1A on Zero
              EPwm1Regs.AQCTLA.bit.CAU = 1;                // Clear PWM1A on event A, up count
    
              //SOCA to ADC
              EPwm1Regs.ETSEL.bit.SOCAEN=1;
              EPwm1Regs.ETSEL.bit.SOCASEL=1;
              EPwm1Regs.ETPS.bit.SOCAPRD = 1;
              EPwm1Regs.ETCLR.bit.SOCA = 1;
              EDIS;
    }
    
    void Init_ADCs(void)
    {
        EALLOW;
                AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
                AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
                AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
    
                AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
                AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
                AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    
                AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                DELAY_US(1000);
    
                AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
                AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
                AdccRegs.ADCCTL2.bit.PRESCALE = 6;
    
                AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin A0
                AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;  //SOC1 will convert pin A1
                AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin A2
                AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC3 will convert pin A3
                AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;  //SOC4 will convert pin A4
                AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;  //SOC5 will convert pin A5
    
                AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin B2
                AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin B3
                AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4;  //SOC2 will convert pin B4
                AdcbRegs.ADCSOC3CTL.bit.CHSEL = 5;  //SOC3 will convert pin B5
    
                AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin C2
                AdccRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin C3
                AdccRegs.ADCSOC2CTL.bit.CHSEL = 4;  //SOC2 will convert pin C4
                AdccRegs.ADCSOC3CTL.bit.CHSEL = 5;  //SOC3 will convert pin C5
    
    
                AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
                AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
                AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
    
                AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
                AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
                AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    
        EDIS;
    }

    I am wondering how the PWM is being regulated without the extsync trigger!

    I gave a thought on your recommendation and I reckon, the ePWM1 would anyway generates the SYNCOUT to the next peripheral at CTR=0. My problem is the ePWM is not at all reacting with the EXTSYNCIN1!

    Thanks in advance.

    Regards,

    Rajesh.

  • Hi Rajesh,

    Thanks for the follow up. The purpose of the EXSYNCOUT would be to check the external sync-in source is passing through. You can set up the EPWM1 so that it only syncs from an external sync source. In this way, you would be able to ensure the external sync is being passed to the EPWM as expected.

    You can also monitor the status of the synchronization being received:

    Can you please send scope captures of your waveform as well as the external signal you are trying to sync to and the EXTSYNCOUT of EPWM1? Are you able to see the SYNCI bit set as well?

    Best Regards,

    Allison

  • Hi Allison,

    Tried your recommendation and I dont see any pulses at GPIO6(muxed to EXTSYNCOUT). I am uploading the video of the 2 pulses(ePWM1A and ext trigger)

    #include "F28x_Project.h"
    
    extern void InitSysCtrl(void);
    extern void InitPieCtrl(void);
    extern void InitPieVectTable(void);
    
    interrupt void TimerOvf(void);
    interrupt void ADCs_EOC(void);
    
    void Initialize_GPIO(void);
    void Custom_Init(void);
    void timer0_init(void);
    void PWM1_Init(void);
    void Init_ADCs(void);
    void X_bar(void);
    
    int b=0;
    float a=0;
    
    
    void main(void)
    {
    
       InitSysCtrl();
       Custom_Init();
       PWM1_Init();
       Init_ADCs();
    
       DINT;
       Initialize_GPIO();
       InitPieCtrl();
    
       IER = 0x0000;
       IFR = 0x0000;
       InitPieCtrl();
       InitPieVectTable();
    
       EALLOW;
       PieCtrlRegs.PIEIER1.bit.INTx1 = 1;    //ADC-A1
       PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
       PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
    
    
       PieVectTable.TIMER0_INT = &TimerOvf;
       PieVectTable.ADCA1_INT = &ADCs_EOC;
       PieCtrlRegs.PIECTRL.bit.ENPIE= 1;
       EDIS;
    
       IER |= 3;
       EINT;  // Enable Global interrupt INTM
       ERTM;  // Enable Global realtime interrupt DBGM
       timer0_init();
       CpuTimer0Regs.TCR.bit.TSS=0;
       while(1)
           {
    
            }
    }
    void Initialize_GPIO(void)
    {
        EALLOW;
        GpioCtrlRegs.GPADIR.bit.GPIO10 = 0;
        GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
        GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
        GpioCtrlRegs.GPCDIR.bit.GPIO73= 1;
        GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //EPwm1
        GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; //EPwm2
    
        EDIS;
    
    }
    void Custom_Init(void)
    {
        EALLOW;
        ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL=1;
        ClkCfgRegs.AUXPLLMULT.bit.IMULT=20;
        ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
        ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
        ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
        ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
        CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;   ///source initsysctrl
        CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
        CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
        CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
        DevCfgRegs.CPUSEL0.bit.EPWM1 = 0;
        EDIS;
    }
    
    
    void timer0_init(void)
    {
        EALLOW;
        CpuTimer0Regs.PRD.bit.MSW = 0x0004;
        CpuTimer0Regs.PRD.bit.LSW = 0x0080;
        CpuTimer0Regs.TPR.bit.TDDR = 0x0013;
    
    
        CpuTimer0Regs.TCR.bit.TIE= 1;
        CpuTimer0Regs.TCR.bit.TSS=1;
        CpuTimer0Regs.TCR.bit.FREE=0;
        CpuTimer0Regs.TCR.bit.TRB=0;
        EDIS;
    }
    void TimerOvf(void)
    {
        b= b+1;
    
        if(b>3)
        {
            EPwm1Regs.TBSTS.bit.SYNCI=1;
    
            b=1;
        }
        if(EPwm1Regs.TBSTS.bit.SYNCI==1)
        {
            GpioDataRegs.GPBSET.bit.GPIO34=1;
            GpioDataRegs.GPASET.bit.GPIO31=1;
        }
    
    
        CpuTimer0Regs.TCR.bit.TIF = 1;
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }
    
    void ADCs_EOC(void)
    {
    
        a = AdcaResultRegs.ADCRESULT0; //Va
        EPwm1Regs.CMPA.bit.CMPA = 10000*a/4095;
        EPwm2Regs.CMPA.bit.CMPA = 10000*a/4095;
        EPwm4Regs.CMPA.bit.CMPA = 10000*a/4095;
    
        AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
        PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    }
    
    void X_bar(void)
    
    {
        EALLOW;
    
        InputXbarRegs.INPUT5SELECT = 10;
        SyncSocRegs.SYNCSELECT.bit.SYNCOUT = 0; //EPWMSYNCOUT select
        GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3;
        GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
        SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = 5;
        GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 3; //ext syncout at GPIO6
      //  GpioDataRegs.GPASET.bit.GPIO10 = 1;
      //  GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
    
        EDIS;
    
    }
    
    void PWM1_Init(void)
    {
              EALLOW;
    
              EPwm1Regs.TBCTL.bit.CTRMODE = 0;             // Count up
              EPwm1Regs.TBPRD = 10000;                    // Set timer period
              EPwm1Regs.TBCTL.bit.PHSEN = 1;               // Enable phase loading
              EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;          // Phase is 0
              EPwm1Regs.TBCTR = 0x0000;                    // Clear counter
              EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;           // Clock ratio to SYSCLKOUT
              EPwm1Regs.TBCTL.bit.CLKDIV = 0;
              EPwm1Regs.TBCTL.bit.SYNCOSEL = 0;
              // Setup shadow register load on ZERO
              EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
              EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
              EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
              EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
              // Set Compare values
                    // Set compare A value
              // Set actions
              EPwm1Regs.AQCTLA.bit.ZRO = 2;                // Set PWM1A on Zero
              EPwm1Regs.AQCTLA.bit.CAU = 1;                // Clear PWM1A on event A, up count
    
              //SOCA to ADC
              EPwm1Regs.ETSEL.bit.SOCAEN=1;
              EPwm1Regs.ETSEL.bit.SOCASEL=1;
              EPwm1Regs.ETPS.bit.SOCAPRD = 1;
              EPwm1Regs.ETCLR.bit.SOCA = 1;
    
    
    
              EPwm2Regs.TBCTL.bit.CTRMODE = 0;             // Count up
              EPwm2Regs.TBPRD = 10000;                    // Set timer period
              EPwm2Regs.TBCTL.bit.PHSEN = 1;               // Enable phase loading
              EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;          // Phase is 0
              EPwm2Regs.TBCTR = 0x0000;                    // Clear counter
              EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;           // Clock ratio to SYSCLKOUT
              EPwm2Regs.TBCTL.bit.CLKDIV = 0;
              EPwm2Regs.TBCTL.bit.SYNCOSEL = 0;
              // Setup shadow register load on ZERO
              EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;
              EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0;
              EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;
              EPwm2Regs.CMPCTL.bit.LOADBMODE = 0;
              // Set Compare values+
                    // Set compare A value
              // Set actions
              EPwm2Regs.AQCTLA.bit.ZRO = 2;                // Set PWM1A on Zero
              EPwm2Regs.AQCTLA.bit.CAU = 1;                // Clear PWM1A on event A, up count
    
    
              EPwm4Regs.TBCTL.bit.CTRMODE = 0;             // Count up
              EPwm4Regs.TBPRD = 10000;                    // Set timer period
              EPwm4Regs.TBCTL.bit.PHSEN = 1;               // Enable phase loading
              EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;          // Phase is 0
              EPwm4Regs.TBCTR = 0x0000;                    // Clear counter
              EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0;           // Clock ratio to SYSCLKOUT
              EPwm4Regs.TBCTL.bit.CLKDIV = 0;
              EPwm4Regs.TBCTL.bit.SYNCOSEL = 0;
                // Setup shadow register load on ZERO
              EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;
              EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;
              EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;
              EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;
                // Set Compare values
                      // Set compare A value
                // Set actions
              EPwm4Regs.AQCTLA.bit.ZRO = 2;                // Set PWM1A on Zero
              EPwm4Regs.AQCTLA.bit.CAU = 1;                // Clear PWM1A on event A, up count
    
              EDIS;
    }
    
    void Init_ADCs(void)
    {
        EALLOW;
                AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
                AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
                AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
    
                AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
                AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
                AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
    
                AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
                DELAY_US(1000);
    
                AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
                AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
                AdccRegs.ADCCTL2.bit.PRESCALE = 6;
    
                AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;  //SOC0 will convert pin A0
                AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;  //SOC1 will convert pin A1
                AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;  //SOC2 will convert pin A2
                AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;  //SOC3 will convert pin A3
                AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;  //SOC4 will convert pin A4
                AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5;  //SOC5 will convert pin A5
    
                AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin B2
                AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin B3
                AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4;  //SOC2 will convert pin B4
                AdcbRegs.ADCSOC3CTL.bit.CHSEL = 5;  //SOC3 will convert pin B5
    
                AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;  //SOC0 will convert pin C2
                AdccRegs.ADCSOC1CTL.bit.CHSEL = 3;  //SOC1 will convert pin C3
                AdccRegs.ADCSOC2CTL.bit.CHSEL = 4;  //SOC2 will convert pin C4
                AdccRegs.ADCSOC3CTL.bit.CHSEL = 5;  //SOC3 will convert pin C5
    
    
                AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdcbRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
                AdccRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
    
                AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
                AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
                AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1;
                AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
                AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
    
    
                AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
                AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;   //enable INT1 flag
                AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
    
        EDIS;
    }
    

    You can see the extpulse(blue) and ePWM1A(yellow) are not locked!

    Thanks in advance.

    Regards,

    Rajesh.

  • Hi Rajesh,

    Thanks for your follow up and efforts. I'm going to take a closer look at your configurations and see if I can test them out. I'll let you know as soon as I do, but please allow until Monday for me to get back to you at latest. Appreciate the patience!

    Best Regards,

    Allison

  • Hi Allison!

    The issue has been resolved. It was actually a silly mistake- didnt called the Xbar initialization function. The ePWM1A is now synchronized with the external trigger, however, the ADC stopped getting triggered by the ePWM1A now.

    Here is the newthread for the new issue.

    (1) TMS320F28379D: ADC not getting triggered by ePWM while ePWM is being external synch triggered - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums

    Regards,

    Rajesh.

  • Hi Rajesh,

    Great to hear the syncing was resolved! Thanks for posting a new thread, I will let the assigned ADC expert answer your query there.

    Best Regards,

    Allison