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TMS320F280049C: CLA MMOV32 conditional move instruction vs. post increment addressing, behaviour, pipeline and documentation unclear

Carl Schlockermann
Prodigy 20 points
Part Number: TMS320F280049C

Tool/software:

I'm reading myself into the CLA instruction set and find conditional move instructions quite handy, especially

MMOV32 MRa, mem32 {, CNDF}

I assume flags are evaluated in the EXE stage and MRa is only written if the condition is true. Regarding the move, there is no problem with the pipeline.

But what happens if mem32 is indirect addressing with post increment (*MAR0[#imm16]++)?

a) is this post increment also conditional or always executed, since the whole instruction is conditional?

b) if conditional, MAR post-increment is written in the D2 phase, so flags would need to be evaluated in the D1 or D2 phase in addition?

Would be nice if one could answer the question and update the documentation regarding this point.

Conditional post increment would allow conditional calculations within MARx, but I fear such MARx calculations are not conditional but always executed.

  • 0
    TI__Mastermind 19595 points

    Hi Carl,

    This is something I will need to consult the design and compiler teams about, as I am not able to find the answer in any documentation (as you have mentioned). Please allow me some time to look into this with them and I will get back to you.

    For now, if you want to try something, you can open the Disassembly window in the debugger and monitor and see what the behavior is depending on the conditional (Maybe have the code write the MRA0 register contents to a memory location for monitoring since I don't believe you will have access to the register directly).

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 20 points

    Hi Delaney,

    thanks for looking into the documentation.

    In the meantime I found a way around it, but this takes a few extra cycles (and calculating addresses as float feels weird).

    I honestly didn't find the time to try this:

        MMOV16    MAR0, #0
        MMOV32     MR1, #1.0
        MMOV32    MR0, #0.0
        MCMP32    MR0, MR1
        MNOP
        MNOP
        MNOP
        MMOV32  MR0, *MAR0[1]++, GT
        MCMP32  MR1, MR0
        MMOV32  MR0, *MAR0[2]++, GT
        MMOV32  MR0, *MAR0[4]++, GT
        MMOV32  MR0, *MAR0[8]++, GT
        MMOV32  MR0, *MAR0[16]++, GT
        MMOV16    @Result, MAR0

    'Result' should show if and when MAR0 is modified conditional.

    I first wrote the functionality in C and used the compiler, but it was far from perfect or fast. The compiler is not using those conditional moves at all but is always jumping around with many MNOPs to clear the pipeline.

    Best regards,

    Carl

  • 0 in reply to Carl Schlockermann
    TI__Mastermind 19595 points

    Hi Carl,

    Unfortunately, I have not been able to find any more resources about the CLA Instruction set internally, so the best information I can offer is what is in the TRM as far as instruction behavior goes. This is a very specific case, which I believe is why we don't have it documented. The best solution would be to step through the disassembly and view the MAR0 registers in the debugger to understand the behavior.

    Best Regards,

    Delaney 

  • 0 in reply to Delaney Woodward
    TI__Mastermind 19595 points

    Another note: to improve compiler performance, you can also try enabling Optimizations in your project properties which could get rid of the MNOPs in some cases.