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Original question:

TIDM-02000: Query Regarding Slope Compensation in 3kW DC/DC Converter Design (Based on TIDM-02000)

TIDM-02000: Slope Compensation for Peak Current Mode Control (PCMC)

Abdur Rehman
Prodigy 20 points
Part Number: TIDM-02000
Other Parts Discussed in Thread: PMP23126

Tool/software:

Hello, 

We are developing a DC/DC converter based on TI reference design (TIDM-02000).

Queries:

1. Is there any formula or method to determine the slope value for the ramp compensation in PCMC (input current of the FB).

2. How to select the burden resistor for PCMC (Please note that we want to sense the currrent up to 165% of the Prated)?

More details (for Query 1) are as follows:

<1>. Please note that the current (Iinput) is sensed at the input side of the PSFB (marked with red in the below picture), NOT the transformer primary current (Ipri).

<2>. I am sharing three cases to explain our problem.

case 1: For 100% load, slope m1 is selected.

Case 2: For 100% load, slope m2 (>m1) is selected.

Case 3: For 150% load, slope m2 is used.

For case 3, with higher slope value (m2) and at higher loads (>100%, e.g., 150% Prated), the reference current (generated by the voltage controller) saturates to max current value.

as a result, under case 3, the converter experiences large steady-state error in the output voltage. Therefore, a higher value of the m2 slope is difficult to be determined.

More details (for Query 2) are as follows:

We tried changing the current transformer burden resistor (R2 in below diagram) value in order to increase the range of the sensed current. 

<Secondary-side circuitry of the sense current tranformer>

Here, we are interested in calcuating the exact value of R2 for our application. Is there any specific guideline for burden resistor calculation.

Currently, we are using the following logic to calculate R2 and R1 values.

1. R2 is calculated considering the maximum converter current and the voltage limit of DSP (3.3V). We used R = V/I.

2. R1 is 100x of R2 value.

However, due to incorrect slope compensation value, the value of sensed current doesn't seems to be sufficient. 

<**>. Additional Information:

In the custom design, we made some changes, including but not limited to:

1. Switching frequency: 55kHz

2. Rated Power level 3.2kW

Thank you

Regards

  • 0
    TI__Mastermind 29511 points

    Regarding your first query. The slope value is determined empirically as described in the design guide. Here you are mainly concerned that the slope is not so high that the ramp will decrease faster than your comparator period.

    I believe the way to think about this is the fact that energy is transferred to the load during the overlap of the lagging and leading PWMs. Therefore, you want to make sure the phase angle between the PWMs is as close to 180 degrees as possible during high loads. Yes, the slope will have some influence here, but assuming the slope is not something huge, other settings like blanking windows and dead band configuration will be more important.

    Regarding your second query, I don't specific guidance. You could look at the current waveform to determine if your current sensing circuit is giving you a good sensing range. 

  • 0 in reply to Gus Martinez
    Prodigy 20 points

    We would appreciate if you can share some document regarding slope compensation calculations, as we are required to calculate the exact slope value for our solution.

    The TI design notes and other documents do not provide detailed derivation steps.

    Thank you

  • +1 in reply to Abdur Rehman
    TI__Mastermind 29511 points

    You can review PMP23126 user guide (found in https://www.ti.com/tool/C2000WARE-DIGITALPOWER-SDK). There is more information on slope compensation there.