TMS320F280039C-Q1: CLA cannot read the variables in LS RAM properly

//###########################################################################
//
// FILE:     device_cla.c
//
// TITLE:   f28003x CPU 32-bit Timers Initialization & Support Functions.
//
//###########################################################################
//
//
// $Copyright:
// Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
//
// $
//###########################################################################


#include "device.h"





void Device_initCla(void)
{
    // Initialize and wait for MEMCFG_SECT_LS0
    MemCfg_initSections(MEMCFG_SECT_LS0);
    while(MemCfg_getInitStatus(MEMCFG_SECT_LS0) != 1);

    // Initialize and wait for MEMCFG_SECT_LS1
    MemCfg_initSections(MEMCFG_SECT_LS1);
    while(MemCfg_getInitStatus(MEMCFG_SECT_LS1) != 1);

    // Initialize and wait for MEMCFG_SECT_LS2
    MemCfg_initSections(MEMCFG_SECT_LS2);
    while(MemCfg_getInitStatus(MEMCFG_SECT_LS2) != 1);

#if DEVICE_IO == DEVICE_IO_OBC
    // Initialize and wait for MEMCFG_SECT_LS3
    MemCfg_initSections(MEMCFG_SECT_LS3);
    while(MemCfg_getInitStatus(MEMCFG_SECT_LS3) != 1);

    // Initialize and wait for MEMCFG_SECT_LS4
    MemCfg_initSections(MEMCFG_SECT_LS4);
    while(MemCfg_getInitStatus(MEMCFG_SECT_LS4) != 1);
#endif

    EALLOW ;

#ifdef _FLASH
    //
    // Copy CLA code from its load address (FLASH) to CLA program RAM
    //
    // Note: during debug the load and run addresses can be
    // the same as Code Composer Studio can load the CLA program
    // RAM directly.
    //
    // The ClafuncsLoadStart, ClafuncsLoadEnd, and ClafuncsRunStart
    // symbols are created by the linker.
    //
    memcpy((uint32_t *)&Cla1funcsRunStart, (uint32_t *)&Cla1funcsLoadStart,
            (uint32_t)&Cla1funcsLoadSize);

    memcpy((uint32_t *)&Cla1ConstRunStart, (uint32_t *)&Cla1ConstLoadStart,
            (uint32_t)&Cla1ConstLoadSize);

    memcpy((uint32_t *)&Cla1mathTablesRunStart, (uint32_t *)&Cla1mathTablesLoadStart,
            (uint32_t)&Cla1mathTablesLoadSize);
#endif


    // Initialize and wait for CLA1ToCPUMsgRAM
    MemCfg_initSections(MEMCFG_SECT_MSGCLA1TOCPU);
    while(MemCfg_getInitStatus(MEMCFG_SECT_MSGCLA1TOCPU) != 1);

    // Initialize and wait for CPUToCLA1MsgRAM
    MemCfg_initSections(MEMCFG_SECT_MSGCPUTOCLA1);
    while(MemCfg_getInitStatus(MEMCFG_SECT_MSGCPUTOCLA1) != 1);

#if DEVICE_IO == DEVICE_IO_DCDC
    // CLA Program will reside in RAMLS0 and data in RAMLS1, RAMLS2
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS2, MEMCFG_LSRAMMASTER_CPU_CLA1);
//    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS3, MEMCFG_LSRAMMASTER_CPU_CLA1);
//    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS4, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_PROGRAM);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_PROGRAM);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS2, MEMCFG_CLA_MEM_DATA);
//    MemCfg_setCLAMemType(MEMCFG_SECT_LS3, MEMCFG_CLA_MEM_PROGRAM);
//    MemCfg_setCLAMemType(MEMCFG_SECT_LS4, MEMCFG_CLA_MEM_DATA);
#elif DEVICE_IO == DEVICE_IO_OBC
    // CLA Program will reside in RAMLS0 and data in RAMLS1, RAMLS2
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS0, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS1, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS2, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS3, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setLSRAMMasterSel(MEMCFG_SECT_LS4, MEMCFG_LSRAMMASTER_CPU_CLA1);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS0, MEMCFG_CLA_MEM_PROGRAM);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS1, MEMCFG_CLA_MEM_PROGRAM);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS2, MEMCFG_CLA_MEM_PROGRAM);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS3, MEMCFG_CLA_MEM_PROGRAM);
    MemCfg_setCLAMemType(MEMCFG_SECT_LS4, MEMCFG_CLA_MEM_DATA);
#endif
    //
    // Suppressing #770-D conversion from pointer to smaller integer
    // The CLA address range is 16 bits so the addresses passed to the MVECT
    // registers will be in the lower 64KW address space. Turn the warning
    // back on after the MVECTs are assigned addresses
    //
#pragma diag_suppress = 770
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_1, (uint16_t)(&Cla1Task1));
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_2, (uint16_t)(&Cla1Task2));
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_3, (uint16_t)(&Cla1Task3));
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_4, (uint16_t)(&Cla1Task4));
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_5, (uint16_t)(&Cla1Task5));
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_6, (uint16_t)(&Cla1Task6));
    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_7, (uint16_t)(&Cla1Task7));
//    CLA_mapTaskVector(CLA1_BASE, CLA_MVECT_8, (uint16_t)(&Cla1Task8));
    CLA_mapBackgroundTaskVector(CLA1_BASE, (uint16_t)(&Cla1Task8));     // ����8����Ϊ��̨����
#pragma diag_suppress = 770

    //
    // Enable the IACK instruction to start a task on CLA in software
    // for all  8 CLA tasks. Also, globally enable all 8 tasks (or a
    // subset of tasks) by writing to their respective bits in the
    // MIER register
    //
    CLA_enableIACK(CLA1_BASE);
    CLA_enableTasks(CLA1_BASE, CLA_TASKFLAG_ALL);

    // Enable ADCC2 INT trigger for CLA TASK1
    //CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_ADCC2);
    //CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_EPWM4INT);
    CLA_setTriggerSource(CLA_TASK_1, CLA_TRIGGER_ADCB1);

#if DEVICE_IO == DEVICE_IO_DCDC
//     Enable ECAP1 INT trigger for CLA TASK2
    CLA_setTriggerSource(CLA_TASK_2, CLA_TRIGGER_ECAP1INT);
    CLA_setTriggerSource(CLA_TASK_3, CLA_TRIGGER_ECAP2INT);
    CLA_setTriggerSource(CLA_TASK_4, CLA_TRIGGER_ECAP3INT);

#endif

    // Enable BackgroundTask
    CLA_enableBackgroundTask(CLA1_BASE);
    CLA_forceTasks(CLA1_BASE,CLA_TASKFLAG_8);
    CLA_startBackgroundTask(CLA1_BASE);

    EDIS;
}


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// End of File
//