F29H850TU: EtherCAT - Share Clock with PHYs, recommendations and tradeoffs

Hello Kevin,

I have concluded my testings.

My experiment is to compare the jitter on the ESC_PHY_CLK signal to the Buffered Clock signal on the F29H85X-SOM-EVM.

As a first step, I had to establish the clock source (the external oscillator) is stable, else it could propagate and induce false conclusions later.

I used a small GPS module with a 1 pulse-per-second to provide a precise clock source, connect it to GPIO77 and used an ECAP to continually measure the period of the pulse. Basically, it counts for 200M clock pulse, self reset and continue.

Having a min/max average, I was able to have this:

minimum: 199998564
maximum: 199998607
average: 199998578
Number of pulses: 6065

So, over 101 minutes, I had a static offset of 200e6-199998578= 1422 pulses per second.
1422/200e6 = 7.2ppm.

The frequency spread is 199998607-199998564= 43
43/200e6=0.2ppm

I concluded that the clock is precise and with very minimal spead.

==

Second part of the experiment is to compare clocks:

ESC_CLK_PHY (Again, why is it names ETHERCATPHYCLK here?) is activated on GPIO54, probed on R31
Buffered Out is probed on R32
XCLKOUT is activated on GPIO219, probed on R44.
Note my test made XCLKOUT go to 200MHz, above the 50MHz maximum from the datasheet. It did work, well enough for this test. Of course signal was clipped and sinusoidal instead of a perfect square wave.

I probed the three signals with a scope, with infinite persistence, triggered on the Clock Buffered output.
Let it run for a while.

Blue = ESC_PHY_CLK
Yellow = Clock Buffered Output
Green = XCLKOUT on PLLSYSCLK

The real goal is ton compare the Bufferd Out to the ESC_PHY_CLK. As the former is the source and the later is going trough some transformations. Any anomalies on ESC_PHY_CLK would have been introduced by those transformations.

This screenshot is after 30 minutes. I also ran it to 4 hours with the same result, but lost the screenshot. Note my green probe is a bit wacky and banging the table made the measure jumps in amplitude, and note that at those frequency, probing techniques are super important and I neglected most of them, resulting in less-than-perfect square waves. I also suspect some crosstalk between my probes. Please don't judge ;).

What does this screenshot tells me?

- The PLLSYSCLK is very jitter-stable. I am not expecting it to "skip beats" of any sort. Blue rise/fall is not moving around.
- ESC_PHY_CLK is almost perfectly in phase with the Clock Buffer. PLL and other dividers introduces little delay.
- There is no observable jitter on ESC_PHY_CLK. The blue line "persistence smear" during the rise and fall is minimal.

Beckhoff calls for three criterion to make a clock suitable for EtherCAT PHYs in "Application note – PHY selection guide" V3.0:
 - ESC and PHY shall share the same clock source
 - ESC and PHY may have a phase shift difference in the clock, but that phase shift shall stay constant
 - ESC and PHY clock shall have no greater than 25ppm error at room temperature. 

==

This experiment allow me to conclude that the ESC_PHY_CLK outputs are stable and precise. The diagram clearly shows the clock is a branch from PLLCLK shared directly between the ESC module and the ESC_PHY_CLK outputs.

There seems to be no weird jitter injected from passing trough a PLL-ized clock.

We also did run the EtherCAT loopback exemple with the ESC_PHY_CLK as a shared source with success.

Kevins' previous comment "I know of other customers having success using ESC_PHY_CLK on other C2000 devices" confirms that I'm not a lunatic.

With all this, I will press on and use the ESC_PHY_CLK as a PHY clock source in our upcoming design, and I urge TI to soften the wording on the documentation, and maybe even ditch the clock buffer on future SOMs.... or provide more guidance if any concerns remains.

Thanks!