TMS320F2800137: F2800137 Global load of AQCTLA

Arnaud,

Even if you manually set AQCTL in code it will get overwritten by sysconfig if its not set there. That maybe the issue behind global loading not working. Did you try C2000 ware example on ePWM global load example number 14 located C:\ti\c2000\C2000Ware_5_04_00_00\driverlib\f280013x\examples\epwm\CCS? Please take a look at that example, sysconfig and comments for explanation. 

Regards,

Sumit

Hi,

I am using global loading a lot already without any issue with most CMP/TPRD registers. But due to some new requirement for PWM, I need to change also AQCTLA but need to be loaded at 0 after I do set OSHTL.

From the example 14,

1- why do you not set Shadow mode for Action Qualifier for ePWM2 and 3 but only on ePWM1? Should I do that for Global load?

2- Why do you also need to set "Force Load Event" in Global Load setting for PWM2 and 3? (I also do use link with ePWM1 for global load)

Thanks, 

Hi,

The problem may be related to question below.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1057414/tms320f280049-how-to-clear-gldctl2-oshtld

The issue that I have is when using OSHTLD when the control loop (fixe frequency, NOT PWM ISR) is running close too the same frequency as the PWMs and the OSHTLD is set very close to or around counter 0.

It seems that when I set OSHTLD, it is possible that at the next control calculation, I update shadow register even before the OSHTLD was executed making only next PWM cycle to be not as expected (only half updated). Can it be a valid cause?

I suppose that there is nothing to prevent updates of shadow registers if OSHTLD was set but not executed as it seems that we can only read OSHTLD as 0.

In this case, what do you propose as a solution to make sure that we do not update shadow registers until the reload was effectively executed in Global Load Mode?

Thanks,
Arnaud

Forgot to say that PWM are variable frequency but control is fixe.

Hi Arnaud,

Just to make sure my understanding is correct. There are 2 ISRs - One is control ISR which is fixed frequency where the control effort is computed.

There is another ISR which is PWM ISR where the values are written into PWM registers. Is this correct? and this PWM ISR is variable frequency and triggered at CTR zero for example?

You are seeing the issue when the PWM frequency is more than the control frequency? Is this for LLC topology? We can also share how we have implemented based on the topology of interest.

Best regards, Pawan

HI,

Can you  please refer to https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1469372/tms320f2800137-f2800137-hrpwm-and-one-shot-load-mode/5645487#5645487 [e2e.ti.com]

It seems to be that some shadow registers (not all) are been partially updated while the PWM is transferring shadow to main at 0 cntr. Causing the next PWM cycle not to be as expected.

Thanks,

Arnaud

Hi Arnaud,

Based on the discussion on the other thread.

• It seems there is not sufficient time to update all the PWM registers at 400kHz+ ISR. Is it possible to make the PWM ISR the highest priority?
• Another method is to check the TBPRD register, see if there are sufficient clock cycles remaining to update the PWM registers. Only if sufficient cycles are available then write into the PWM registers. Do you think this would work out for your application?

Best regards, Pawan

Hi Pawan,

The PWM ISR is the highest priority. I do not have any other ISR except if there is the hardware overcurrent signal but should only run during specific conditions.

Since power supply (GaN) can run at very high rate of frequency (up to 1MHz), what is your best solution to synchronized control loop and PWM updates?

Is checking TBPRD the best solution for high frequency application? or is there any other that you propose?

Thanks,

Arnaud

Arnaud,

I have found that when switching frequency is higher than control frequency all the time lets say we are running ISR at 100kHz all the time and PWM frequency (PRD) is always >100kHz then one shot loading will work fine because it can synchronize with next ePWM zero. Issue appears when Fsw < Fctrl when control will be asynchronously update the period using one shot load especially when there are are multiple leg topology and if its ePWMs are phase shifted when zero is happening at different times. One of the solution can be as you suggested, implement the logic that checks TBPRD and then let go respective ePWM cycle depend on how much lower you are trying to go for fsw with respect to fctrl before you update ePWM registers and ePWM1.GLDCTL2.OSHTLD bit.

If its okay for you, may I know what specific type of topology or waveform pattern you are tying to implement here so that we can think of if there is any workaround?

Regards,

Sumit