TMS320F28388D: Accessing peripheral result by both the cores simultaneously

YEDIDA AYYAPPA RUDRASIMHA

Tool/software:

Hi Team,

I have activated adc ISR and ecap3 ISR in both the cores. I am reading the result of eCAP module in both the cores and using for control purpose. I have the following questions,

1. Can the both cores access the eCAP result (ECap3Regs.CAP1) at the same time? If they access at same time, what can happen to the result read by both the cores as it can trigger ecap event at same time to both the cores?

2. If I have configured the same interrupt in both the events like ecap3_isr,adc_isr,pwm_isr then do I need to acknowledge in both the cores like below?

    EALLOW;
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP4);
    ECAP_clearInterrupt(ECAP3_BASE,ECAP_ISR_SOURCE_CAPTURE_EVENT_1);
    ECAP_clearInterrupt(ECAP3_BASE,ECAP_ISR_SOURCE_CAPTURE_EVENT_2);
    ECAP_clearInterrupt(ECAP3_BASE,ECAP_ISR_SOURCE_CAPTURE_EVENT_3);
    ECAP_clearInterrupt(ECAP3_BASE,ECAP_ISR_SOURCE_CAPTURE_EVENT_4);
    ECAP_clearGlobalInterrupt(ECAP3_BASE);
    ECap3Regs.ECCLR.bit.INT = 0x1;
    EDIS;

3. If adc result is read by CPUs, before the result ready or during conversion, will it be previous value or random value?

over 1 year ago

0 Ryan Ma over 1 year ago

TI__Mastermind 27736 points

YEDIDA AYYAPPA RUDRASIMHA said:
1. Can the both cores access the eCAP result (ECap3Regs.CAP1) at the same time? If they access at same time, what can happen to the result read by both the cores as it can trigger ecap event at same time to both the cores?

Both cores cannot access the eCAP result at the same time. Which core has access to the peripheral registers will be determined by the CPUSEL register. Please refer to this e2e thread: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/881378/tms320f28379d-access-to-the-peripherals

For example, if CPU1 owns eCAP1, then only CPU1 will be able to read from the eCAP registers. CPU2 will read back 0's. Even though both cores can be triggered by the same interrupt source.

YEDIDA AYYAPPA RUDRASIMHA said:
2. If I have configured the same interrupt in both the events like ecap3_isr,adc_isr,pwm_isr then do I need to acknowledge in both the cores like below?

Yes each CPU has their own PIPE. Thus, making sure to get the next interrupt on each core means you'll need to acknowledge both.

YEDIDA AYYAPPA RUDRASIMHA said:
If adc result is read by CPUs, before the result ready or during conversion, will it be previous value or random value?

The ADC results are duplicated for each CPU, CLA, and DMA so that no arbitration is needed when reading the result registers. If ADC result is read by CPUs before the result is read, it will contain previous value.

Best,

Ryan Ma

0 YEDIDA AYYAPPA RUDRASIMHA over 1 year ago in reply to Ryan Ma

Prodigy 140 points

1. Can it be accessed sequentially? I think I was able to see the ecap result "ECap3Regs.CAP1" in both the cores. I will check and confirm.

2. As ownership assigned to only one CPU, only that CPU can clear ecap ECCLR right? so only group level acknowledgment in both the cores?

0 Ryan Ma over 1 year ago in reply to YEDIDA AYYAPPA RUDRASIMHA

TI__Mastermind 27736 points

YEDIDA AYYAPPA RUDRASIMHA said:
1. Can it be accessed sequentially? I think I was able to see the ecap result "ECap3Regs.CAP1" in both the cores. I will check and confirm.

Please check and confirm. I have also tested this, and CPU2 read back 0's when reading from eCAP registers when eCAP1 belonged to CPU1.

YEDIDA AYYAPPA RUDRASIMHA said:
As ownership assigned to only one CPU, only that CPU can clear ecap ECCLR right? so only group level acknowledgment in both the cores?

That's correct. Only group level acknowledgement in both the cores for the PIE.

Best,

Ryan Ma

0 YEDIDA AYYAPPA RUDRASIMHA over 1 year ago in reply to Ryan Ma

Prodigy 140 points

Thanks for the quick response. I am out station, I will check and confirm once I am back. If the both CPUs needs to access ecap result register, Is it only can be done by through sending the ecap result through IPC or any other method through which we can access the ecap result owned by other CPU?

0 Ryan Ma over 1 year ago in reply to YEDIDA AYYAPPA RUDRASIMHA

TI__Mastermind 27736 points

That's correct, would be to use IPC or any other method such as shared RAM.

Best,

Ryan Ma

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TMS320F28388D: Accessing peripheral result by both the cores simultaneously