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Tool/software:
Hi team,
I ask this for my customer, they use EPWM2 is the source of sync signal and the EPWM1 is slave. the configuration is show in this
/**********************************************************************
Copyright 2022,valeo Corporation.
File Name: BspEpwm.c
Description: BspEpwm
Version: V1.0
Author: deyi.chen
Date: 2022-11-25
***********************************************************************/
/* header files ***************************************************************/
#include "include.h"
#include "sfo_v8.h"
/* local macro definitions ****************************************************/
#define myEPWM1_BASE EPWM1_BASE
#define myEPWM2_BASE EPWM2_BASE
#define myEPWM3_BASE EPWM3_BASE
#define myEPWM4_BASE EPWM4_BASE
/* local types definitions ****************************************************/
/* local variable declarations ************************************************/
/* global variable declarations ***********************************************/
boolean_t BspPWM_bTZTriggerFlag;
/* internal function prototypes ***********************************************/
int MEP_ScaleFactor; // Global variable used by the SFO library
// Result can be used for all HRPWM channels
// This variable is also copied to HRMSTEP
// register by SFO() function.
uint16_t status;
volatile uint32_t ePWM[] =
{0, myEPWM1_BASE,myEPWM2_BASE,myEPWM3_BASE,myEPWM4_BASE};
//
// Function Prototypes
//
void error(void);
void vidInitBspEPwm1Regs(void);
void vidInitBspEPwm2Regs(void);
void vidInitBspEPwm3Regs(void);
void vidInitBspEPwm4Regs(void);
void vidInitBspEPwm5Regs(void);
void vidInitACRelayDriver(void);
void vidInitBspEPwm7Regs(void);
void BspPWM_vidAllPwmDisable(void);
void BspPWM_vidDABPWMTZConfig(void);
//*********************************************************************
//Function name: void BspPWM_vidInit(void)
//Description: BspPWM_vidInit
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidInit(void)
{
// Calling SFO() updates the HRMSTEP register with calibrated MEP_ScaleFactor.
// HRMSTEP must be populated with a scale factor value prior to enabling
// high resolution period control.
//
while(status == SFO_INCOMPLETE)
{
status = SFO();
if(status == SFO_ERROR)
{
/*error(); */ // SFO function returns 2 if an error occurs & # of MEP
} // steps/coarse step exceeds maximum of 255.
}
EALLOW;
// Disable TBCLK before EPWM Initialization
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
vidInitBspEPwm1Regs();
vidInitBspEPwm2Regs();
vidInitBspEPwm3Regs();
vidInitBspEPwm4Regs();
vidInitACRelayDriver(); //ACRelay_Driver_PWM_Config
vidInitBspEPwm7Regs();
BspPWM_vidDABPWMTZConfig();
EALLOW;
// Enable TBCLK after EPWM Initialization
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EPwm1Regs.TBCTL.bit.SWFSYNC = 1;
EPwm2Regs.TBCTL.bit.SWFSYNC = 1;
EPwm3Regs.TBCTL.bit.SWFSYNC = 1;
EPwm4Regs.TBCTL.bit.SWFSYNC = 1;
EPwm5Regs.TBCTL.bit.SWFSYNC = 1;
EDIS;
}
//*********************************************************************
//Function name: void BspPWM_vidInitGpio(void)
//Description: The power frequency bridge arm is initialized as output,
// and the high frequency bridge arm is initialized as input.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidInitGpio(void)
{
EALLOW;
//***************************** Driver Gate Enable***************************
//GPIO7------Disable PFC driver signal GATE_SLOW_H/GATE_SLOW_L, GATE_FAST_H1/GATE_FAST_L1
//Diable the rectifier
GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 0; //selecct as PFC_Driver output gate
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; //selecct as GPIO
GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
/*GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; */ //0 Disable
//GPIO5------Disable LLC_SW_PRI_ENA GATE_PRI_LL/GATE_PRI_LH/GATE_PRI_RL/GATE_PRI_RH
GpioCtrlRegs.GPAGMUX1.bit.GPIO5 = 0; //selecct as LLC Driver output gate
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0; //selecct as GPIO
GpioCtrlRegs.GPADIR.bit.GPIO5 = 1; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
GpioDataRegs.GPACLEAR.bit.GPIO5 = 1;
GpioCtrlRegs.GPACSEL1.bit.GPIO5 = 0x01; //CLA Need Init
//GPIO61------LLC_SW_SEC_ENA GATE_SEC_LL/GATE_SEC_LH/GATE_SEC_RL/GATE_SEC_RH
GpioCtrlRegs.GPBGMUX2.bit.GPIO61 = 0; //selecct as LLC Driver output gate
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 0; //selecct as GPIO
GpioCtrlRegs.GPBDIR.bit.GPIO61 = 1; //Direction is input
GpioCtrlRegs.GPBPUD.bit.GPIO61 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1;
GpioCtrlRegs.GPBCSEL4.bit.GPIO61 = 0x01; //CLA Need Init
//*****************************Driver****************************************
//GATE_PRI_LH------EPWM1A
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0; //PFC_FAST_H1_EPWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; //PFC_FAST_H1_EPWM1A
GpioCtrlRegs.GPADIR.bit.GPIO0 = 0; //0 Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; //Low Level
//GATE_PRI_LL------EPWM1B
GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 0; //PFC_FAST_L1_EPWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; //PFC_FAST_L1_EPWM1B
GpioCtrlRegs.GPADIR.bit.GPIO1 = 0; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; //Low Level
//GATE_PRI_RH------EPWM2A
GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0; //PFC_FAST_H2_EPWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; //PFC_FAST_H2_EPWM2A
GpioCtrlRegs.GPADIR.bit.GPIO2 = 0; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; //Low Level
//GATE_PRI_RL------EPWM2B
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0; //PFC_FAST_L2_EPWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; //PFC_FAST_L2_EPWM2B
GpioCtrlRegs.GPADIR.bit.GPIO3 = 0; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; //Low Level
//GATE_SEC_LH------EPWM3A
GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 0; //PFC_FAST_H2_EPWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; //PFC_FAST_H2_EPWM3A
GpioCtrlRegs.GPADIR.bit.GPIO14 = 0; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; //Pull-up disabled, pull-up disabled or enabled
//only works for open-drain output
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1; //Low Level
//GATE_SEC_LL------EPWM3B
GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 0; //PFC_FAST_L2_EPWM3B
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; //PFC_FAST_L2_EPWM3B
GpioCtrlRegs.GPADIR.bit.GPIO15 = 0; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO15 = 1; //Low Level
//GATE_SEC_RH-------EPWM4A
GpioCtrlRegs.GPAGMUX2.bit.GPIO22= 0; //GATE_SEC_RH_EPWM4A
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; //GATE_SEC_RH_EPWM4A
GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; //Low Level
//GATE_SEC_RL-------EPWM4B
GpioCtrlRegs.GPAGMUX2.bit.GPIO23= 0; //GATE_SEC_RL_EPWM4B
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; //GATE_SEC_RL_EPWM4B
GpioCtrlRegs.GPADIR.bit.GPIO23 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO23 = 1; //Low Level
//
//GATE_FAST_H1/GATE_SLOW_L-------EPWM5A
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0; //GATE_SEC_RH_EPWM5A
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0; //GATE_SEC_RH_EPWM5A
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; //Low Level
//GATE_SLOW_H/GATE_FAST_L1-------EPWM5B
GpioCtrlRegs.GPAGMUX1.bit.GPIO9= 0; //GATE_SEC_RL_EPWM5B
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; //GATE_SEC_RL_EPWM5B
GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; //Low Level
//*****************************Relay Driver**************************************
//GPIO10-----AC relay driver (PWM needed_20K)
GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 0; //Relay_Driver_20K_EPWM5B
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; //Relay_Driver_20K_EPWM5B
GpioCtrlRegs.GPADIR.bit.GPIO10 = 0; //Direction is input
GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; //Pull-up disabled
EDIS;
}
//*********************************************************************
//Function name: void vidInitBspPwmPFCFAST1(void)
//Description: PFC_FAST1_PWM_Config GLDCTL Register
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitBspEPwm1Regs(void)
{
//config counter mode
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm1Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
/*EPwm1Regs.EPWMSYNCOUTEN.bit.ZEROEN = SYNC_OUT_SRC_ENABLE;*/
EPwm1Regs.EPWMSYNCINSEL.bit.SEL = EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2;
/*EPWM_setupEPWMLinks(myEPWM1_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_TBPRD);*/
//config TBCLK
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;
EPwm1Regs.TBPHS.bit.TBPHS = 1;
EPwm1Regs.TBCTR = 0;
//config CMP
EPwm1Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;
EPwm1Regs.CMPB.bit.CMPB = 0;
//config shadow register, load CMP when CTR == 0
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
/*New*/
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;// DB_ACTV_HIC; // Active Hi Complimentary
EPwm1Regs.DBRED.bit.DBRED = BspPWM_DAB_DIEDTIME;
EPwm1Regs.DBFED.bit.DBFED = BspPWM_DAB_DIEDTIME;
EPwm1Regs.AQSFRC.bit.RLDCSF = CC_CTR_ZERO; //Config Action Qualifier Register
/*Global*/
EPWM_enableGlobalLoadRegisters(myEPWM1_BASE, EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_CMPA_CMPAHR);
EPWM_setGlobalLoadTrigger(myEPWM1_BASE, EPWM_GL_LOAD_PULSE_SYNC);
EPWM_setGlobalLoadEventPrescale(myEPWM1_BASE, 1);
EPWM_enableGlobalLoad(myEPWM1_BASE);
EPWM_setupEPWMLinks(myEPWM1_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_TBPRD);
EPWM_setupEPWMLinks(myEPWM1_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_A);
/*
EPWM_setupEPWMLinks(myEPWM1_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_A);
EPWM_enableGlobalLoadRegisters(myEPWM1_BASE, EPWM_GL_REGISTER_CMPA_CMPAHR);
*/
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on
// both edges.
EPwm1Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR
// HR control.
EPwm1Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // load on CTR = 0
// and CTR = TBPRD
EPwm1Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on
// both edges
EPwm1Regs.HRCNFG.bit.CTLMODEB = HR_CMP; // CMPBHR and TBPRDHR
// HR control
EPwm1Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO; // load on CTR = 0
// and CTR = TBPRD
EPwm1Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for
// HR period
EPwm1Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
// (required for updwn
// count HR control)
EPwm1Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution
// period control.
EDIS;
}
//*********************************************************************
//Function name: void vidInitBspEPwm2Regs(void)
//Description: vidInitBspEPwm2Regs config. No phase shift at the initial time.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitBspEPwm2Regs(void)
{
//config counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm2Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
EPwm2Regs.EPWMSYNCOUTEN.bit.ZEROEN = SYNC_OUT_SRC_ENABLE;
/*EPwm2Regs.EPWMSYNCINSEL.bit.SEL = EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1;*/
//config TBCLK
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD;
EPwm2Regs.TBPHS.bit.TBPHS = 1;
EPwm2Regs.TBCTR = 0;
//config CMP
EPwm2Regs.CMPA.bit.CMPA = EPWM2_MIN_CMPA;
EPwm2Regs.CMPB.bit.CMPB = 0;
//config shadow register, load CMP when CTR == 0
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
/*New*/
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;// DB_ACTV_HIC; // Active Hi Complimentary
EPwm2Regs.DBRED.bit.DBRED = BspPWM_DAB_DIEDTIME;
EPwm2Regs.DBFED.bit.DBFED = BspPWM_DAB_DIEDTIME;
EPwm2Regs.AQSFRC.bit.RLDCSF = CC_CTR_ZERO; //Config Action Qualifier Register
/*Global*/
EPWM_enableGlobalLoadRegisters(myEPWM2_BASE, EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_CMPA_CMPAHR);
EPWM_setGlobalLoadTrigger(myEPWM2_BASE, EPWM_GL_LOAD_PULSE_CNTR_ZERO);
EPWM_setGlobalLoadEventPrescale(myEPWM2_BASE, 1);
EPWM_enableGlobalLoad(myEPWM2_BASE);
/*EPWM_setupEPWMLinks(myEPWM1_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_GLDCTL2);*/
/*HR*/
/*
EALLOW;
EPwm2Regs.HRCNFG.all = 0x0;
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on
// both edges.
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_PHS; // TBPHSHR
// Phase control.
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // load on CTR = 0
EPwm2Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on
// both edges
EPwm2Regs.HRCNFG.bit.CTLMODEB = HR_PHS; // TBPHSHR
EPwm2Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO; // load on CTR = 0
// and CTR = TBPRD
EPwm2Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for
// HR period
EPwm2Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
// (required for updwn
// count HR control)
EPwm2Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution
// period control.
EDIS;
*/
}
//*********************************************************************
//Function name: void vidInitBspEPwm2Regs(void)
//Description: vidInitBspEPwm2Regs config. No phase shift at the initial time.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitBspEPwm3Regs(void)
{
//config counter mode
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm3Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm3Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
EPwm3Regs.EPWMSYNCINSEL.bit.SEL = EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2;
/*EPWM_setupEPWMLinks(myEPWM3_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_TBPRD);*/
//config TBCLK
EPwm3Regs.TBPRD = EPWM2_TIMER_TBPRD;
EPwm3Regs.TBPHS.bit.TBPHS = 1;
EPwm3Regs.TBCTR = 0;
//config CMP
EPwm3Regs.CMPA.bit.CMPA = EPWM2_MIN_CMPA;
EPwm3Regs.CMPB.bit.CMPB = 0;
//config shadow register, load CMP when CTR == 0
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
/*New*/
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;// DB_ACTV_HIC; // Active Hi Complimentary
EPwm3Regs.DBRED.bit.DBRED = BspPWM_DAB_DIEDTIME;
EPwm3Regs.DBFED.bit.DBFED = BspPWM_DAB_DIEDTIME;
/*Global*/
EPWM_enableGlobalLoadRegisters(myEPWM3_BASE, EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_CMPA_CMPAHR);
EPWM_setGlobalLoadTrigger(myEPWM3_BASE, EPWM_GL_LOAD_PULSE_SYNC);
EPWM_setGlobalLoadEventPrescale(myEPWM3_BASE, 1);
EPWM_enableGlobalLoad(myEPWM3_BASE);
EPWM_setupEPWMLinks(myEPWM3_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_TBPRD);
EPWM_setupEPWMLinks(myEPWM3_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_A);
EPwm3Regs.AQSFRC.bit.RLDCSF = CC_CTR_ZERO; //Config Action Qualifier Register
/*Global*/
/*
EPWM_enableGlobalLoad(myEPWM3_BASE);
EPWM_setupEPWMLinks(myEPWM3_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_GLDCTL2);
EPWM_enableGlobalLoadRegisters(myEPWM3_BASE, EPWM_GL_REGISTER_TBPRD_TBPRDHR);
EPWM_setGlobalLoadTrigger(myEPWM3_BASE, EPWM_GL_LOAD_PULSE_CNTR_PERIOD);
*/
/*HR*/
EALLOW;
EPwm3Regs.HRCNFG.all = 0x0;
EPwm3Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on
// both edges.
EPwm3Regs.HRCNFG.bit.CTLMODE = HR_PHS; // TBPHSHR
// Phase control.
EPwm3Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // load on CTR = 0
EPwm3Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on
// both edges
EPwm3Regs.HRCNFG.bit.CTLMODEB = HR_PHS; // TBPHSHR
EPwm3Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO; // load on CTR = 0
// and CTR = TBPRD
EPwm3Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for
// HR period
EPwm3Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
// (required for updwn
// count HR control)
EPwm3Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution
// period control.
EDIS;
}
//*********************************************************************
//Function name: void vidInitBspEPwm2Regs(void)
//Description: vidInitBspEPwm2Regs config. No phase shift at the initial time.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitBspEPwm4Regs(void)
{
//config counter mode
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm4Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
EPwm4Regs.EPWMSYNCINSEL.bit.SEL = EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2;
/*EPWM_setupEPWMLinks(myEPWM4_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_TBPRD);*/
//config TBCLK
EPwm4Regs.TBPRD = EPWM2_TIMER_TBPRD;
EPwm4Regs.TBPHS.bit.TBPHS = 1;
EPwm4Regs.TBCTR = 0;
//config CMP
EPwm4Regs.CMPA.bit.CMPA = EPWM2_MIN_CMPA;
EPwm4Regs.CMPB.bit.CMPB = 0;
//config shadow register, load CMP when CTR == 0
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
/*New*/
EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;// DB_FULL_ENABLE;
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;// DB_ACTV_HIC; // Active Hi Complimentary
EPwm4Regs.DBRED.bit.DBRED = BspPWM_DAB_DIEDTIME;
EPwm4Regs.DBFED.bit.DBFED = BspPWM_DAB_DIEDTIME;
/*Global*/
EPWM_enableGlobalLoadRegisters(myEPWM4_BASE, EPWM_GL_REGISTER_TBPRD_TBPRDHR | EPWM_GL_REGISTER_CMPA_CMPAHR);
EPWM_setGlobalLoadTrigger(myEPWM4_BASE, EPWM_GL_LOAD_PULSE_SYNC);
EPWM_setGlobalLoadEventPrescale(myEPWM4_BASE, 1);
EPWM_enableGlobalLoad(myEPWM4_BASE);
EPWM_setupEPWMLinks(myEPWM4_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_TBPRD);
EPWM_setupEPWMLinks(myEPWM4_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_COMP_A);
EPwm4Regs.AQSFRC.bit.RLDCSF = CC_CTR_ZERO; //Config Action Qualifier Register
/*Global*/
/*
EPWM_enableGlobalLoad(myEPWM4_BASE);
EPWM_setupEPWMLinks(myEPWM4_BASE, EPWM_LINK_WITH_EPWM_2, EPWM_LINK_GLDCTL2);
EPWM_enableGlobalLoadRegisters(myEPWM4_BASE, EPWM_GL_REGISTER_TBPRD_TBPRDHR);
EPWM_setGlobalLoadTrigger(myEPWM4_BASE, EPWM_GL_LOAD_PULSE_CNTR_PERIOD);
*/
/*HR*/
EALLOW;
EPwm4Regs.HRCNFG.all = 0x0;
EPwm4Regs.HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on
// both edges.
EPwm4Regs.HRCNFG.bit.CTLMODE = HR_PHS; // TBPHSHR
// Phase control.
EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // load on CTR = 0
EPwm4Regs.HRCNFG.bit.EDGMODEB = HR_BEP; // MEP control on
// both edges
EPwm4Regs.HRCNFG.bit.CTLMODEB = HR_PHS; // TBPHSHR
EPwm4Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO; // load on CTR = 0
// and CTR = TBPRD
EPwm4Regs.HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion for
// HR period
EPwm4Regs.HRPCTL.bit.TBPHSHRLOADE = 1; // Enable TBPHSHR sync
// (required for updwn
// count HR control)
EPwm4Regs.HRPCTL.bit.HRPE = 1; // Turn on high-resolution
// period control.
EDIS;
}
//*********************************************************************
//Function name: void vidInitBspEPwm5Regs(void)
//Description: vidInitBspEPwm5Regs Only use to trigger the ADC
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitBspEPwm5Regs(void)
{
//config counter mode
EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm5Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm5Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm5Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
EPwm5Regs.EPWMSYNCINSEL.bit.SEL = EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1;
//config TBCLK
EPwm5Regs.TBPRD = EPWM5_TIMER_TBPRD;
EPwm5Regs.TBPHS.bit.TBPHS = 0;
EPwm5Regs.TBCTR = 0;
//config CMP
EPwm5Regs.CMPA.bit.CMPA = EPWM5_TIMER_TBPRD>>1;
EPwm5Regs.CMPB.bit.CMPB = 0;
//config shadow register, load CMP when CTR == 0
EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
//Config Action Qualifier Register
EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR; //Output high level, when TBCTR=CMPA raise edge
EPwm5Regs.AQCTLA.bit.CAD = AQ_SET; //Output low level, when TBCTR=CMPA fall edge
EPwm5Regs.AQCTLB.bit.CAU = AQ_SET; //Output low level, when TBCTR=CMPA raise edge
EPwm5Regs.AQCTLB.bit.CAD = AQ_CLEAR; //Output high level, when TBCTR=CMPA fall edge
//Config Deadband Register
EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL; //Dead zone input mode control bit, 0 indicates that EPWMxA
//is used as the signal source at the falling edge and rising edge
EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //Polarity Select Control, 2 means high compensation mode, EPWMxB flip
EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //Dead Band Output Mode Control 3 means that the dead zone
//enables the rising edge delay output of EPWMxA, and the falling edge delay output of EPWMxB
EPwm5Regs.DBRED.bit.DBRED = BspPWM_DAB_DIEDTIME; //rising edge time delay
EPwm5Regs.DBFED.bit.DBFED = BspPWM_DAB_DIEDTIME; //falling edge time delay
}
//*********************************************************************
//Function name: void vidInitACRelayDriver(void)
//Description: ACRelay_Driver_PWM_Config
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitACRelayDriver(void)
{
//config TBCLK
EPwm6Regs.TBPRD = EPWM6_TIMER_TBPRD;
EPwm6Regs.TBPHS.bit.TBPHS = 0;
EPwm6Regs.TBCTR = 0;
//config CMP
EPwm6Regs.CMPA.bit.CMPA = EPWM6_MAX_CMPA;
EPwm6Regs.CMPB.bit.CMPB = 0;
//config counter mode
EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm6Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
//EPwm5Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
//config shadow register, load CMP when CTR == 0
EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//Config Action Qualifier Register
EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; //Output high level, when TBCTR=CMPA
EPwm6Regs.AQCTLA.bit.CAD = AQ_SET; //Output low level, when TBCTR=CMPA
}
//*********************************************************************
//Function name: void vidInitBspEPwm7Regs(void)
//Description: For PWM interrupt and ADC trigger
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void vidInitBspEPwm7Regs(void)
{
//config counter mode
EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm7Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;
EPwm7Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;
EPwm7Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
EPwm7Regs.TBCTL.bit.SWFSYNC = TB_CTR_ZERO;
//EPwm7Regs.EPWMSYNCOUTEN.bit.ZEROEN = SYNC_OUT_SRC_ENABLE;
//config TBCLK
EPwm7Regs.TBPRD = EPWM7_TIMER_TBPRD;
EPwm7Regs.TBPHS.bit.TBPHS = 0;
EPwm7Regs.TBCTR = 0;
//config CMP
EPwm7Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;
EPwm7Regs.CMPB.bit.CMPB = 0;
//config shadow register, load CMP when CTR == 0
EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
//Config Action Qualifier Register
EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; //Output high level, when TBCTR=CMPA raise edge
EPwm7Regs.AQCTLA.bit.CAD = AQ_SET; //Output low level, when TBCTR=CMPA fall edge
EPwm7Regs.AQCTLB.bit.CAU = AQ_SET; //Output low level, when TBCTR=CMPA raise edge
EPwm7Regs.AQCTLB.bit.CAD = AQ_CLEAR; //Output high level, when TBCTR=CMPA fall edge
//Config Deadband Register
EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL; //Dead zone input mode control bit, 0 indicates that EPWMxA
//is used as the signal source at the falling edge and rising edge
EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; //Polarity Select Control, 2 means high compensation mode, EPWMxB flip
EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //Dead Band Output Mode Control 3 means that the dead zone
//enables the rising edge delay output of EPWMxA, and the falling edge delay output of EPWMxB
EPwm7Regs.DBRED.bit.DBRED = BspPWM_DAB_DIEDTIME; //rising edge time delay
EPwm7Regs.DBFED.bit.DBFED = BspPWM_DAB_DIEDTIME; //falling edge time delay
EPwm7Regs.ETSEL.bit.INTEN = 0; /* Enable PWM1 interrupt */
EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; /* Trigger interrupt at CTR = 0 and CTR = PRD */
EPwm7Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm7Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO /*ET_CTR_PRD*/; // Use CBU event as trigger
EPwm7Regs.ETPS.bit.SOCAPRD = ET_1ST;
EPwm7Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
EPwm7Regs.ETSEL.bit.INTEN = 1;
}
/*DAB priamary gate*/
//*********************************************************************
//Function name: void BspPWM_vidDABPriDriveGateEnable(void)
//Description: IO control, high level means enable.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABPriDriveGateEnable(void)
{
GpioDataRegs.GPASET.bit.GPIO5 = 1; //GATE_PRI_LL/GATE_PRI_LH/GATE_PRI_RL/GATE_PRI_RH
}
//*********************************************************************
//Function name: void BspPWM_vidDABPriDriveGateDisable(void)
//Description: IO control, low level means disable.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABPriDriveGateDisable(void)
{
GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; //GATE_PRI_LL/GATE_PRI_LH/GATE_PRI_RL/GATE_PRI_RH
}
/*DAB Secondary gate*/
//*********************************************************************
//Function name: void BspPWM_vidDABSecDriveGateEnable(void)
//Description: IO control, high level means enable.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABSecDriveGateEnable(void)
{
GpioDataRegs.GPBSET.bit.GPIO61 = 1; //GATE_SEC_LL/GATE_SEC_LH/GATE_SEC_RL/GATE_SEC_RH
}
//*********************************************************************
//Function name: void BspPWM_vidDABSecDriveGateDisable(void)
//Description: IO control, low level means disable.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABSecDriveGateDisable(void)
{
GpioDataRegs.GPBCLEAR.bit.GPIO61 = 1; //GATE_SEC_LL/GATE_SEC_LH/GATE_SEC_RL/GATE_SEC_RH
}
/*DAB PWM Enable and Disable*/
//*********************************************************************
//Function name: void BspPWM_vidDABPrimaryLeftDisable(void)
//Description: BspPWM_vidDABPrimaryLeftDisable,Configure related pins as IO functions
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABPrimarySidePwmDisable(void)
{
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0; //GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; //disable internel pullup
GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 0; //GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; //disable internel pullup
GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0; //GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; //disable internel pullup
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0; //GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; //disable internel pullup
EDIS;
}
//*********************************************************************
//Function name: void BspPWM_vidDABSecondaryLeftDisable(void)
//Description: BspPWM_vidDABSecondaryLeftDisable,Configure related pins as IO functions
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABSecondarySidePwmDisable(void)
{
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 0; //GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO14 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO14 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; //disable internel pullup
GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 0; //GPIO
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO15 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO15 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; //disable internel pullup
GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 0; //GPIO
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO22 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO22 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; //disable internel pullup
GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 0; //GPIO
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; //GPIO
GpioDataRegs.GPACLEAR.bit.GPIO23 = 1; //output low level
GpioCtrlRegs.GPADIR.bit.GPIO23 = 1; //output
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; //disable internel pullup
EDIS;
}
//*********************************************************************
//Function name: void BspPWM_vidDABPrimarySidePwmEnable(void)
//Description: BspPWM_vidDABPrimarySidePwmEnable
// GPIO0/EPWM1A/PIN79 -> GATE_PRI_LH
// GPIO1/EPWM1B/PIN78 -> GATE_PRI_LL
// GPIO2/EPWM2A/PIN77 -> GATE_PRI_RH
// GPIO3/EPWM2B/PIN76 -> GATE_PRI_RL
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABPrimarySidePwmEnable(void)
{
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 0; //EnableEPwm1A
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 0; //EnableEPwm1B
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 0; //EnableEPwm2A
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 0; //EnableEPwm2B
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1;
EDIS;
}
//*********************************************************************
//Function name: void BspPWM_vidDABSecondarySidePwmEnable(void)
//Description: BspPWM_vidDABSecondarySidePwmEnable,
// GPIO14/EPWM3_A/PIN96 -> GATE_SEC_LH
// GPIO15/EPWM3_B/PIN95 -> GATE_SEC_LL
// GPIO22/EPWM4A/PIN83 -> GATE_SEC_RH
// GPIO23/EPWM4B/PIN81 -> GATE_SEC_RL
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABSecondarySidePwmEnable(void)
{
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; //EnableEPwm3A
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; //EnableEPwm3B
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1;
GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 3; //EnableEPwm4A
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2;
GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 3; //EnableEPwm4B
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2;
EDIS;
}
/*Rectifier gate*/
//*********************************************************************
//Function name: void vidBspPFCPwmOutputEnable(void)
//Description: vidBspPFCPwmOutputEnable,PFC_SW_ENA
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
/*
void vidBspRECPwmOutputEnable(void)
{
GpioDataRegs.GPASET.bit.GPIO7 = 1;
}*/
//*********************************************************************
//Function name: void vidBspPFCPwmOutputDisable(void)
//Description: vidBspPFCPwmOutputDisable,PFC_SW_ENA
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
/*void vidBspRECPwmOutputDisable(void)
{
GpioDataRegs.GPACLEAR.bit.GPIO7 = 1;
}*/
/*Rectifier Driver*/
//*********************************************************************
//Function name: void BspPWM_vidOpenPFCPowerSlowFreqUp(void)
//Description: IO control, high level means enable. PWM use the Gpio Control
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
/*void BspPWM_vidRECPwmLeftEnable(void)
{
GpioDataRegs.GPASET.bit.GPIO8 = 1; //GATE_FAST_H1/GATE_SLOW_L
}*/
//*********************************************************************
//Function name: void BspPWM_vidOpenPFCPowerSlowFreqDown(void)
//Description: IO control, high level means enable. PWM use the Gpio Control
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
/*
void BspPWM_vidRECPwmRightEnable(void)
{
GpioDataRegs.GPASET.bit.GPIO9 = 1; //GATE_SLOW_H/GATE_FAST_L1
}*/
//*********************************************************************
//Function name: void BspPWM_vidClosePFCPowerSlowFreq(void)
//Description: IO control, low level means off
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
/*
void BspPWM_vidRECPwmDisable(void)
{
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO9 = 1;
}*/
//*********************************************************************
//Function name: void BspPWM_vidAllPwmDisable(void)
//Description: All pwm drive off.
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidAllPwmDisable(void)
{
BspPWM_vidDABPrimarySidePwmDisable();
BspPWM_vidDABSecondarySidePwmDisable();
//BspPWM_vidRECPwmDisable();
}
//*********************************************************************
//Function name: void BspPWM_vidRECPwmConfigAsPWM(void)
//Description: Config the REC Gpio as PWM function
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidRECPwmConfigAsEPwm(void)
{
EALLOW;
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0; //EnableEPwm5A
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;
GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 0; //EnableEPwm5B
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;
EDIS;
}
//*********************************************************************
//Function name: void BspPWM_vidRECPwmConfigAsPWM(void)
//Description: Config the REC Gpio as PWM function
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidRECPwmConfigAsGpio(void)
{
EALLOW;
/*GATE_FAST_H1/GATE_SLOW_L-------EPWM5A*/
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0; //GATE_SEC_RH_EPWM5A
GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 0; //GATE_SEC_RH_EPWM5A
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO8 = 1; //Low Level
/*GATE_SLOW_H/GATE_FAST_L1-------EPWM5B*/
GpioCtrlRegs.GPAGMUX1.bit.GPIO9= 0; //GATE_SEC_RL_EPWM5B
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; //GATE_SEC_RL_EPWM5B
GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; //Direction is output
GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; //Pull-up disabled
GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; //Low Level
EDIS;
}
//*********************************************************************
//Function name: BspPWM_vidSetCompareValue(uint32_t base, EPWM_CompareModule compModule, Uint16 compCount)
//Description: BspPWM_vidSetCompareValue
//Calls: none
//Called By: none
//Parameters: base:PWMx EPWM_CompareModule:EPWM_COMPARE_X compCount:CMP
//Return: void
//*********************************************************************
void BspPWM_vidSetCompareValue(uint32_t u32Base, EPWM_CompareModule compModule, Uint16 u16CompCount)
{
uint32_t u32RegisterOffset = 0;
u32RegisterOffset = (uint32_t)(EPWM_O_CMPA + (Uint16)compModule);
if ( (compModule == EPWM_COMPARE_A) || (compModule == EPWM_COMPARE_B) )
{
(*((volatile Uint16 *)(u32Base + u32RegisterOffset + 0x1U))) = u16CompCount;
}
else
{
(*((volatile Uint16 *)(u32Base + u32RegisterOffset))) = u16CompCount;
}
}
//*********************************************************************
//Function name: BspPWM_tenuPFCControlLaw_OnFlag BspPWM_enuGetPFCControlLawOnFlag(void)
//Description: BspPWM_enuGetPFCControlLawOnFlag
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
/*
BspPWM_tenuPFCControlLaw_OnFlag BspPWM_enuGetPFCControlLawOnFlag(void)
{
return BspPWM_enuPFCControlLawOnFlag;
}*/
//*********************************************************************
//Function name: void BspPWM_vidPFCTZConfig(void)
//Description: BspPWM_vidPFCTZConfig
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidPFCTZConfig(void)
{
// _____________ __________________
// | | | |
// GPIO52 -----| I/P X-BAR |-----TZ1-----| ePWM TZ Module |-----TZ-Event
// |___________| |________________|
//
EALLOW;
//Pin11 GPIO52 PFC_OCP_FAULT Low_effective
InputXbarRegs.INPUT1SELECT = 52;
EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
// What do we want the DCAEVT1 and DCBEVT1 events to do?
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm1Regs.TZEINT.bit.OST = 1;
EDIS;
}
//*********************************************************************
//Function name: void BspPWM_vidPFCPWMTZIsr(void)
//Description: BspPWM_vidPFCPWMTZIsr
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
interrupt void BspPWM_vidPFCPWMTZIsr(void)
{
BspPWM_bTZTriggerFlag = TRUE;
STM_tenuSystemState enuSystemWorkState = STM_SYSTEMSTATE_IDLE;
enuSystemWorkState = Database_enuGetSystemState();
EALLOW;
//Clear the ePWM1_INT flag to enable further interrupts
EPwm1Regs.TZEINT.bit.OST = 0;
//BspPWM_vidDisableDABPrimaryGpio();
if(EPwm1Regs.TZFLG.bit.OST ==1U)
{
if (enuSystemWorkState == STM_SYSTEMSTATE_DISCHARGE)
{
//Inverter_u16InvCurrOcFlag = 1U;
}
CpuTimer1Regs.TIM.all = (uint32_t)2400;
CpuTimer1Regs.TCR.bit.TSS = 0;
}
else
{
/* Do nothing */
}
EPwm1Regs.TZCLR.bit.INT = 1U;
// Clear PIE acknowledge bit to enable this group interrupt
EDIS;
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP2;
}
//*********************************************************************
//Function name: void BspPWM_vidDABPWMTZConfig(void)
//Description: PWMTZConfig
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidDABPWMTZConfig(void)
{
// _____________ __________________
// | | | |
// GPIO52 -----| I/P X-BAR |-----TZ1-----| ePWM TZ Module |-----TZ-Event
// |___________| |________________|
//
#if 0
// _____________ __________________
// | | | |
// GPIO53 -----| I/P X-BAR |-----TZ2-----| ePWM TZ Module |-----TZ-Event
// |___________| |________________|
//
EALLOW;
//Pin12 GPIO53 LLC_OCP_FAULT Low_effective
InputXbarRegs.INPUT2SELECT = 53;
EPwm7Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;
EPwm8Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;
//EPwm1Regs.TZSEL.bit.
// What do we want the DCAEVT1 and DCBEVT1 events to do?
EPwm7Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm7Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm8Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm8Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm7Regs.TZEINT.bit.OST = 1;
EDIS;
#endif
#if 1
//Just test
EALLOW;
//Pin11 GPIO52 PFC_OCP_FAULT Iac_OCP Low_effective
InputXbarRegs.INPUT1SELECT = 52;
//Pin11 GPIO53 OCP_LLC_FAULT High_effective
InputXbarRegs.INPUT2SELECT = 53;
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWMxA will go low
EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // EPWMxB will go low
EPwm1Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm1Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;
EPwm2Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm2Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;
EPwm3Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm3Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;
EPwm4Regs.TZSEL.bit.OSHT1 = TZ_ENABLE;
EPwm4Regs.TZSEL.bit.OSHT2 = TZ_ENABLE;
EPwm1Regs.TZEINT.bit.OST = 1U;
EPwm1Regs.TZSEL.bit.DCAEVT1 = TZ_DISABLE;
EPwm1Regs.TZSEL.bit.DCBEVT1 = TZ_DISABLE;
EPwm2Regs.TZSEL.bit.DCAEVT1 = TZ_DISABLE;
EPwm2Regs.TZSEL.bit.DCBEVT1 = TZ_DISABLE;
EPwm3Regs.TZSEL.bit.DCAEVT1 = TZ_DISABLE;
EPwm3Regs.TZSEL.bit.DCBEVT1 = TZ_DISABLE;
EPwm4Regs.TZSEL.bit.DCAEVT1 = TZ_DISABLE;
EPwm4Regs.TZSEL.bit.DCBEVT1 = TZ_DISABLE;
EPwm1Regs.DCACTL.bit.EVT1LATSEL = 0x1u;
EPwm1Regs.DCACTL.bit.EVT2LATSEL = 0x1u;
EPwm1Regs.DCBCTL.bit.EVT1LATSEL = 0x1u;
EPwm1Regs.DCBCTL.bit.EVT2LATSEL = 0x1u;
EPwm2Regs.DCACTL.bit.EVT1LATSEL = 0x1u;
EPwm2Regs.DCACTL.bit.EVT2LATSEL = 0x1u;
EPwm2Regs.DCBCTL.bit.EVT1LATSEL = 0x1u;
EPwm2Regs.DCBCTL.bit.EVT2LATSEL = 0x1u;
EPwm3Regs.DCACTL.bit.EVT1LATSEL = 0x1u;
EPwm3Regs.DCACTL.bit.EVT2LATSEL = 0x1u;
EPwm3Regs.DCBCTL.bit.EVT1LATSEL = 0x1u;
EPwm3Regs.DCBCTL.bit.EVT2LATSEL = 0x1u;
EPwm4Regs.DCACTL.bit.EVT1LATSEL = 0x1u;
EPwm4Regs.DCACTL.bit.EVT2LATSEL = 0x1u;
EPwm4Regs.DCBCTL.bit.EVT1LATSEL = 0x1u;
EPwm4Regs.DCBCTL.bit.EVT2LATSEL = 0x1u;
EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;
EPwm3Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;
EPwm3Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;
EPwm4Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_LO;
EPwm4Regs.TZCTL.bit.DCBEVT1 = TZ_FORCE_LO;
EDIS;
#endif
}
//*********************************************************************
//Function name: void BspPWM_vidDABPWMTZIsr(void)
//Description: BspPWM_vidDABPWMTZIsr
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
interrupt void BspPWM_vidDABPWMTZIsr(void)
{
EALLOW;
//Clear the ePWM1_INT flag to enable further interrupts
EPwm1Regs.TZEINT.bit.OST = 0;
Safety_vidSetAlarmBit(AlarmBit_LLCHWCHARGEROCP, TRUE);
//BspPWM_vidDisableDABSecondaryGpio();
EPwm1Regs.TZCLR.bit.INT = 1U;
// Clear PIE acknowledge bit to enable this group interrupt
EDIS;
PieCtrlRegs.PIEACK.all |= PIEACK_GROUP2;
}
//*********************************************************************
//Function name: void BspPWM_vidActionPFCPWMDiriver(Enum_Bsp_Action_PFC_PWM Bsp_Action_PFC_PWM)
//Description: BspPWM_vidActionPFCPWMDiriver
//Calls: none
//Called By: none
//Parameters: void
//Return: void
//*********************************************************************
void BspPWM_vidActionRECPWMDiriver(BspPWM_tenuAction_REC_PWM Bsp_Action_REC_PWM)
{
#if 1
switch(Bsp_Action_REC_PWM)
{
case BspPWM_ACTION_RECPWM_DISABLE:
{
BSPGPIO_REC_PWM_GATE_DISABLE();
}
break;
case BspPWM_ACTION_RECPWM_ENABLE:
{
BSPGPIO_REC_PWM_GATE_ENABLE();
}
break;
default:
BSPGPIO_REC_PWM_GATE_DISABLE();
break;
}
#endif
}
//*********************************************************************
// no more
//*********************************************************************
They use global load and they keep the EPWM1 frequency is 100kHz, the duty is 50%, and they change the phase of EPWM1.
they found if they decrease the lead phase of EPWM1, the first pulse of EPWM1 will lost(the EPWM will out a period high voltage). they do below test:
1. they change the lead phase from 91° to 85.887°, the output of EPWM1 is abnormal.
2.they change the lead phase from 85.887° to 91°, the output of EPWM1 is ok.
Could you give us some suggestion how to do next to find the reason? Could you help to check if the configuration is right? They want to use global load and sync the EPWM1 to EPWM2.
BRs
Shuqing
Hi Shuqing,
Are there any waveforms that can be shared showing the results from the tests above?
For test 1 and 2, the phase shift of EPWM 2 is changed correct? Can I please know the TBPRD value set and the phase value set in the phase registers along with the CMPA values when these tests are done?
Best Regards,
Marlyn
