• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 82 subscribers
  • Views 207 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS320F28379D: PWM Duty extending in multi-phase variable frequency operation

TMS320F280039: Phase-shift & frequency changing PWM, missing pulse

Leo Wu
Intellectual 1410 points
Part Number: TMS320F280039


Tool/software:

Hi experts,

My client is developing Phase-shift & frequency changing function on EPWM1. And meet the issue of missing pulse. (yellow & blue: EPWM1AB; green & purple: EPWM2AB)

The EPWM1 have the same frequency with EPWM2. And EPWM1 receive the SYNC event from EPWM2 (when TBCTR = 0) to load the TBPRD from shadow to active. The EPWM1's TBPRD and CMPA are linking to EPWM2.

EPWM1 and EPWM2 are up-down counting mode. The AQ for them is CMPA-UP: DOWN and CMPA-DOWN: UP. Their duty is 50%. For EPWM2 there is no TBPHS only frequency changing, for EPWM1 there are both TBTHS and frequency changing.

When they changing the the frequency of EPWM from 90k to 70k directly, they will meet the missing pulse events on EPWM1.

We refer to this link: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1312604/tms320f28379d-tms320f28379d-phase-shift-pwm-missing-pulse and add the T1 event with AQ. It will reduce the number of missing pulse events but can not stop missing pulse event.

Are there any other suggestions for this issue?

  • 0
    TI__Mastermind 23840 points

    Hello,

    This is a common occurrence when updating your PWM parameters during run time just due to the nature of when you are updating/loading new values, what those values are, and when a sync pulse occurs. The AQ T1/T2 workaround typically takes care of simpler cases of missed action qualifiers, but I have seen projects where there are other cases that need to be addressed (in one case, for example, I saw a sync pulse occurring between the update of two different PWM parameters within a CLA task which was causing issues of missed AQ that the T1/T2 did not cover. The resolution was to update the parameters back to back within the CLA task to minimize the amount of time between the updates and prevent a sync pulse from occurring in between).

    A few questions:

    1. What parameters are you changing? From your post, my understanding is the following (please correct if I am wrong):
      1. EPWM2: only TBPRD is being updated
      2. EPWM1: TBPRD and TBPHS are being updated
    2. Where are you updating your values (ISR, CLA task, etc.)?
    3. What are your values changing to?
    4. What loading scheme are you using (are the updated parameters loaded in immediate load mode, shadow load mode on some event, or global load on some event)? When are the newly calculated values being loaded to the active registers?
    5. Have you already been scoping out the sync pulse? If not, I would highly recommend using EXTSYNCOUT signal path to be able to scope and see where the sync pulse is happening in relation to where you are updating your parameters (can toggle a GPIO near where you update the parameters as well to have a visual time reference).

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Intellectual 1410 points

    Hi Allison,

    Sorry for reply delay. I take some time to do the test and confirm the situation with the client.

    After checking, I suggest the client to change the CMP value to realize the phase shift with global load and PWM linking.

    For example, the TBPRD for EPWM1 and EPWM2 is 600 (the counter is sync). And CMPA up is 400 and CMPB down is 200 for EPWM1. And CMPA up & down is 300 for EPWM2. So there is a phase shift between EPWM1 and EPWM2. All CMP register, TBPRD register and RED & FED register using shadow register and global load (OSHTLD) (when TBCTR reaches 0). Global load of EPWM1 is linking to EPWM2. So that, we can use OSHTLD bit to load the value to active register at the same time.

    Is this solution ok?

    And here is another question. What will happen, when TBCTR reaches to 0 and write 1 to OSHTLD bit occur at the same time?

    Thanks,

    Leo

  • 0 in reply to Leo Wu
    TI__Mastermind 23840 points

    Hi Leo,

    Please allow another day for me to get back to you on your inquiry. Thanks for your patience!

    Best Regards,

    Allison

  • 0 in reply to Leo Wu
    TI__Mastermind 23840 points

    Hi Leo,

    Sorry for the extended delay. I wanted to check if there was any change/update in the status/information here. Have you already tested and confirmed? Global load would ensure that the variables load at the same time across epwm's, but I would caution to ensure that variables being updated for then next EPWM cycle are updated close together. I have seen an issue where the customer left too much time in between updates and their global load event was occurring in between updates (i.e. half of their PWM updates were being loaded to active registers and half of their PWM updates had not been calculated yet). Their issue was resolved by moving the code where they write to the PWM shadow registers closer together to minimize time in between prepping all shadow registers.

    When is the customer issuing the oneshot global load?

    Best Regards,

    Allison