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TMS320F28379D: Multicore system CLB Ownership and ISRs

Prakhar Gupta
Prodigy 70 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hello,

I am attempting to setup a multicore project that utilizes 3 CLBs to perform some boolean logic on serial data that I receive on a GPIO pin. I have the system tested and working on a single core project. I am curious to learn more about ownership on CLB module instances. There seems to be some conflicting information on the E2E forums, namely:

- CLBx ownership is derived from EPWMx ownership (1<x<4) because the clocks are shared

- Sysctl_selectCPU... can be used to change ownership over the CLB module

However, it seems that the SYSCTL API documentation for c2000ware v5.04.00 has no mention of CLB ownership. Moreover, CLB registers are missing from CPU2 debug view, and are only visible in CPU1 debug view. 

On attempting to use the GUI syscfg tool in an empty multicore project - to add a CLB module to the CPU2 subsytem - the init() code looks identical to what I am doing in my multicore basis - but it is not possible to view the CLB registers from CPU2 debug view.

I would like to know
- Is it even possible to move CLB ownership between the different CPU subsystems?

- Can a CLB belonging to CPU1 be connected to gpio/epwm clk/XBARs that is managed by cpu2?

- Can a CLB belonging to CPU1 have its ISR be in CPU2 (Without raising a CPU1-> CPU2 interrupt)?


  • 0
    Prodigy 70 points

    It is worth noting that I am using EPWM4-12 for driving certain outputs. I would like to use EPWM1 for  a SOC trigger, on CPU subsystem 2. It appears that CLBX initialization works if I do it before setting CPUSEL for CPU2 on EPWMX. However, the CLB configuration (made on CPU1) resets after the ownership is changed. Is there any way to configure CLB1-3 such that EPWM1 is owned by CPU2?

  • 0 in reply to Prakhar Gupta
    TI__Mastermind 28580 points

    Hi Prakhar,

    Please refer to this thread:

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/982088/tms320f28379d-cpusel-for-clb

    Connections between CLB, GPIOs and XBAR are not affected by CPU ownership.

    You may be able to use IPC to trigger a CPU2 interrupt from a CPU1 CLB ISR.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 70 points

    Hi Luke,

    It is still not clear to me if it is possible for CLB module to be managed by CPU2 in the case that the associated EPWM module is already owned by CPU2. 

    Thanks

  • 0 in reply to Prakhar Gupta
    TI__Mastermind 28580 points

    Hi Prakhar,

    I discussed this with other members of the team. I was mistaken, you can allocate CLB1 to CPU2 using the CPUSELx bit and PCLKCRx bit for EPWM1.

    Thank you,

    Luke

  • +1 in reply to Luke Jones
    Prodigy 70 points

    Hi Luke, as per the SYSCTL API documentation - there is no support for setting CPUSELx for the CLB. Moreso, the CPU2 debug view of CCS does not support viewing of CLB Registers

  • 0 in reply to Prakhar Gupta
    TI__Mastermind 28580 points

    Hi Prakhar,

    If EPWM1's CPUSELx bit is set for CPU2, are you still able to configure CLB1 registers via CPU1?

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 70 points

    Hello Luke,

    Apologies for getting back to you this late. TRM mentions 4 Tiles on the f28379d. I assume this is for the entire dsp, and not for each CPU subsystem? The TRM may benefit from an explicit mention of this.


    I have done some testing and have observed some strange behaviors worth noting:

    - When assigning epwm1's CPU sel for CPU2- and then initializing the CLB on CPU2 - there seem to be no changes to the CLB ctrl registers when I init my tile. Additionally, this is hard to verify in debug mode, as CCS does not show the registers for the CLB from CPU2 view. The CLB Regs are at their original startup value when checked from CPU1 view. Furthermore, the HLC ISR (registered and enabled on CPU2) is not triggered

    - When CPUsel for EPWM1 is set for CPU1, and CLB is initialized on CPU1 - the registers are set correctly. This is with the exact same initialization procedure followed in the previous scenario - but done on CPU1. The HLC ISR (registered and enabled on CPU2) is triggered in this case. However, it would appear that the tag information is incorrect (tag is expected to be one, always read 0 in ISR on CPU2)

    - Lastly, when the CPUSEL for EPWM1 is on CPU1, CLB initialization is done on CPU1, and HLC ISR is on CPU1 as well - the tag reads function correctly.



    This leads me to believe that the 4 CLB tiles and associated registers are accessible from CPU1 Subsystem 1 only. Would you be able to confirm this? If this is the case, TRM should mention this - as it can save a lot of development / debug time.

  • 0 in reply to Prakhar Gupta
    TI__Mastermind 28580 points
    Prakhar Gupta said:
    Apologies for getting back to you this late. TRM mentions 4 Tiles on the f28379d. I assume this is for the entire dsp, and not for each CPU subsystem? The TRM may benefit from an explicit mention of this.

    Yes 4 CLBs total on the entire dsp.

    Let me try to test this on my side and share my findings with the team, I think there is some confusion over what CPU "ownership" implies with respect to CLB.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Prodigy 70 points

    Hey Luke. I was wondering if there are any updates?

  • 0 in reply to Prakhar Gupta
    TI__Mastermind 28580 points

    Hi Prakhar,

    I am out of office until tomorrow, will test on my side when I return.

    Thank you,

    Luke