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TMS320F28388D: SPI B channel is not giving correct clock and data width when configured in CPU2 core.

Part Number: TMS320F28388D

Tool/software:

 Hi,
I am developing an SPI driver module for the TMS320F28388D microcontroller,
In one application, I need to use SPI using CPU2 core, so as per guidelines, I had configured SPI GPIO pins 22, 23, 24, and 25 in CPU1 and also set SPIB peripheral master core as CPU2,
Clock config in CPU1: 
 CPU2 master selection settings in CPU1 SYSCTRL module.
After these steps I configured SPIB using Sys Config module in CPU2 as following settings:
Currently I am facing issue with SPI data width, clock configuration here I am expecting as per sys config 16 bit of Data width and 50 KHz should be clock frequency but it never gives continuous clock to show 16 bit of frame format in CPU2. If same sys config settings, I did in CPU1 core that works fine as per expectations.
Attached snaps from logic analyzer for SPI signal observed on HW, please refer those.
SPI communication using CPU2 core.
SPI communication using CPU1 core.
Can anyone please help me to run SPI module using the CPU2 core continuously.