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Original question:

SPI Transmit Interrupt Not Clearing

TMS320F28386D: Not able to clear interruption after configuring TX buffer for SPI

Marta Payá
Prodigy 20 points
Part Number: TMS320F28386D
Other Parts Discussed in Thread: C2000WARE

Tool/software:

I'm configuring my SPI peripheral to work as SPI but after do some staff I need to use it over DMA. If I configure the DMA and after that, the SPI, there is no problem, but if I strat configuring the SPI and after that I configure the DMA is not working. I realised that the problem is the TX interruption is enabled when I enable the SPIFFTX register. But there is no way to clear the interruption, set the TXFFINTCLR register to 1 has no effect.

Please I need a solution.

  • 0
    TI__Genius 16545 points

    Hi Marta,

    Could you clarify if you mean the order of the initialization code for SPI DMA is having an effect on the operation? What configurations are you referring to? It should not matter as long as the initial configurations are done with the modules disabled.

    What are the TX and RX FIFO levels set to? You should only be using the FIFO interrupts not the regular Transmit / Receive interrupts in FIFO mode? The C2000WARE example showcases this flow.

    Best Regards,

    Aishwarya

  • 0 in reply to Aishwarya Rajesh
    Prodigy 20 points

    The behaivour I'm seeing seems related with the register SPIFFTX. It seems the flag TXFFINT is always high, even when I set the TXFFINTCLR register to high, and that flag is used by the DMA to know if there is something to be transmitted. The wrong functionality of this register is doing harder the integration of a new device in my system.

  • 0
    TI__Genius 16545 points

    Marta,

    Have you ran the C2000WARE SPI DMA SW Example? I would follow that flow pretty closely, which it sounds like you may already have been doing.

    I will look into this on my end as well and see if I can reproduce this issue. Let me know if you're able to provide any sample code / configurations for me to take a look at further?

    Best Regards,

    Aishwarya

  • 0
    TI__Genius 16545 points

    Marta,

    Checking in to see if this issue was resolved or you had any other questions.

    In terms of resetting SPI, ensure SPI is disabled when resetting the TX FIFO and clearing all interrupt flags.

    For the FIFO level configuration, set the TXFFIL to the desired trigger level and disable the TXFFIENA. Then, you can configure DMA, enable SPI FIFO, and enable SPI FIFO interrupts.

    Best Regards,

    Aishwarya

  • 0 in reply to Aishwarya Rajesh
    Prodigy 20 points

    Hi Aishwarya,

    I wasn't able to clear the interrupt flag for the SPI FIFO, but I found a workaround to swatich the SPI between regular SPI mode and DMA, so I suppose this issue can be closed.

  • 0
    TI__Genius 16545 points

    Marta,

    Could you post more details on the resolution here for anyone reading this in the future? Thank you!

    Best Regards,

    Aishwarya