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Original question:

TMS320F280037-Q1: Recommended PMIC

TMS320F280037-Q1: PMIC compatibility

Erik Arroyo
Prodigy 50 points
Part Number: TMS320F280037-Q1


Tool/software:

We are using PMIC from a different company, we are checking compatibility, can you please comment on the following?

For power up sequence:

If the slew rate is faster than the specified 8 mV/us, ESD protection can activate, can you please provide details on this protection (what happens to the uC)?.

If slew rate is slower than the specified 100mV/us, the only effect is XRSn toggling, which does not affect microcontroller, only will affect devices connected to XRSn, correct?

For power down sequence:

Are the same effects than power up? if not, can you please provide details for faster and slower than specified slew rate?

For Figure 6-9. Internal VREG Power Up Sequence, the right side (falling edges) represent what is going to happen when the power is going down, the monitors are released, then the micro pulls down reset, is this correct? can micro pull down reset without power?  Is it only in some voltage range while the voltage goes to 0? do you have details?

Any other critical parameters to check compatibility?

  • 0
    TI__Guru* 81500 points
    Erik Arroyo said:
    If the slew rate is faster than the specified 8 mV/us, ESD protection can activate, can you please provide details on this protection (what happens to the uC)?.

    The ESD protection diodes are present to prevent and over/undervoltage condition on the pins from damaging the device.  If the slew rate is faster than what is recommended, then this can cause the diodes to conduct(shorting the pin to VDDIO or VSS), potentially causing damage to the device.  I would take this at face value and make sure the max slew rate is not violated.

    Erik Arroyo said:
    If slew rate is slower than the specified 100mV/us, the only effect is XRSn toggling, which does not affect microcontroller, only will affect devices connected to XRSn, correct?

    Correct, the device itself will never execute any functional code that would impact the system in these conditions.  If the XRSn pin were connected to other ICs(XRSn is an open drain configuration), it would depend on how they require their own XRSn signal to be controlled if this matters.

    Erik Arroyo said:
    For Figure 6-9. Internal VREG Power Up Sequence, the right side (falling edges) represent what is going to happen when the power is going down, the monitors are released, then the micro pulls down reset, is this correct? can micro pull down reset without power?  Is it only in some voltage range while the voltage goes to 0? do you have details?

    This is correct, as soon as we cross the comparison threshold the device will pull XRSn active low, putting the device into reset.  The thresholds are configured as such to not allow the device to be out of reset if the VDDIO voltage would cause the device to be operating out of specification(and hence undefined for the system). 

    At some point ~0.7V the chip will stop driving this as 0V, but at that point none of the transistors on the device are "on" so the device will not be operational anyway.

    Finally, I am assuming you are using the on chip LDO for the 1.2V supply; VREGENZ = 0(or one of the variants where this is permanently enabled). 

    If you are supplying your own 1.2V(VREGENZ=1), the on chip PMM does not monitor that supply with the same precision as the VDDIO, and you have to rely on either the known relationship between the VDDIO/VDD to guarantee that the 1.2V supply is within spec when XRSn is released, or add an external supervisor for VDD.

    Best,

    Matthew