[FAQ] F29x Flash Module & FOTA: Frequently Asked Questions

For reference, please see F29x General FAQ for other IP/peripherals

F29x Flash Module Frequently Asked Questions

What is the flash memory structure on the F29x?

• On the F29H85x, there are 4MB of flash mappable to C29 CPUs (CPU1 and CPU3). These 4MB of flash consist of 4 interleaved bank-pairs with a combined capacity of 1MB each. Each individual bank has 512KB of capacity and is divided into 256 sectors (2KB each). There is also a 256KB dedicated data-only flash bank that is not interleaved and has 128 sectors. The 4MB of CPU-mappable flash supports FOTA. All of the previously mentioned flash memory can be accessed by CPU1, CPU3, the HSM, RTDMA1, and the debugger.

What is the flash memory interleaving scheme on F29x?

• Every 128-bits within a bank-pair alternates which physical flash bank the 128-bits corresponds to. See an example structure below.

What is the difference between a flash sector erase and a flash bank erase on F29x?

• The smallest unit of flash that can be erased is one sector (2 kB). The sector erase command is used to perform a flash erase on a singular sector. The bank erase command is capable of erasing all sectors within a bank and offers Write/Erase protection bitmasks to avoid only erase portions of a bank. It is important to note that individual sector Write/Erase protection granularity is only provided for the first 32 sectors of a bank. Sectors 32-256 (or 128) are broken up into groups of 8 when configuring Write/Erase protection.

What is the provisioning tool?

• Provisioning is the process of securely installing user keys (for root of trust) and code in the device. Provisioning is performed using the TI FlashWriter tool. There are two stages:
  1. Key provisioning: This programs the SMEK, SMPKH, BMPKH and other data into the HSM KEYSTORE region. After this is complete, the device is in HS-KP state. In this state, C29 is blocked from executing Flash code.
  2. Code provisioning: This programs the application code (and authentication certificates) into the HSM and C29 Flash. After this is complete, the device is in HS-SE mode. Secure boot is now enforced and debug ports closed (must be authenticated/opened by HSM RT).
  Request access to F29x TIFS-SDK and OTP Keywriter (within TIFS-SDK) here: https://www.ti.com/tool/F29-SDK 
  README files with documentation for getting started will be located in their respective folders.

How can I combine memory that is non-contingous within a Linker Command File?

• SRAM_LPAx and SRAM_CPAx are contiguous memory regions. You can combine that to a single memory block but you cannot combine 2 non-contiguous memories. Although, you can make the linker allocate sections across multiple memory regions (even non-contiguous ones). In that case, the linker will split the sections and place them across the listed memory regions. You may also refer to the following documentation: TI Linker Command File Primer.

What resources are available for me to learn how to program flash?

• Please refer to the following resources
  • Flash API User's Guide: https://www.ti.com/lit/ug/spruje7a/spruje7a.pdf?ts=1755101092388&ref_url=https%253A%252F%252Fwww.google.com%252F
  • "Flash Module" TRM Chapter: https://www.ti.com/lit/ug/spruj79/spruj79.pdf?ts=1755101179961&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FF29H859TU-Q1
  • Flash Plugin General Usage Guidelines: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1453556/faq-f29h859tu-q1-f29h85x-flash-plugin-usage-notes 

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F29x FOTA Frequently Asked Questions

What is the typical CPU load when an image of firmware is sent through CAN? What is the typical CPU load time during FOTA?

• We do not have any specific/benchmarked numbers for estimated CPU loads during the update process. CPU1 or CPU3 will need to download the update image through CAN. The bank programming process itself is performed by the Flash state machine, so it happens in the background while the CPU is performing other tasks. All the CPU needs to do is poll to check whether the erase/program operation has completed.

What is the step-by-step process of FOTA?

• For FOTA, the bank swapping happens on reset. The device determines which bank should be active based on the BANK_UPDATE_CTR in the BANKMGMT regions of the Flash. Whichever half has a newer version based on the update counter (assuming both are marked as valid) determines the SWAP setting. So, after programming the new image into the update region, the BANKMGMT region needs to be programmed with the BANK_UPDATE_CTR value for the new revision.

For FOTA, when the bank swapping happens on reset:

1. Is this a software reset? Does it work without power off?
2. Is there any specific procedure to issue the reset?
3. Does RAM need to be cleared when a reset is issued?

• The reset referred to here is XRSn. XRSn is controllable by both software and hardware (external pin), and does not require power off (that is PORESETn). XRSn can be initiated in software by writing to the SIMRESET.XRSn register in CPU_SYS_REGS from CPU1. Resets can only be initiated by CPU1 or the HSM. RAM is not automatically cleared on an XRSn reset. It is possible to manually initiate RAM initialization using the memory controller.