Hi experts,
Our KMM co-trust find the issue that the clock output from the 28p65 to the EtherCAT PHY is abnormal.
If they set the configuration as follows:
The clock of PHY will be 50MHz (abnormal), when the chip is at high temperature.
If they set the congurations as follows
The clock of PHY will be 25MHz (normal), when the chip is at high temperature.
They customer wants knows are there any difference between AUXPLL and SYSPLL
Thanks,
Leo
