TMS320F28388D: CLB clock configuration

Jay

Hello, I have referred f28388D TRM, as per TRM CLB clock configuration shown below.

Here as shown there are two inputs 1) AUXPLL 2)SYSCLK
1) which register needs to be configure to define the clock input from above two sources.

2) while in TRM it is showing 2 possible inputs, in syscfg, it only showing AUXPLL as an input

3) By enabling SYNC (via CLKMODECLB1 ), it ensure phase alignment with SYSCLK or some additional features w.r.t. case where SYNC is disabled.

Regards

3 months ago

0 Venkata Praneeth Somina 3 months ago

TI__Intellectual 1160 points

Hi Jay,

1)CLBCLKCTL register in CLK_CFG_REGS need to be configured to define the clock input of a particular instance.
2) This is a bug, will be updated in the next revision. Apologies.
You can use "SysCtl_CLBClkConfig(SysCtl_CLBInst inst, SysCtl_CLBClkm config)" function to select mode of CLB clock.
3)By enabling SYNC mode, it ensures alignment with SYSCLK.

Thanks
Praneeth

0 Jay 3 months ago in reply to Venkata Praneeth Somina

Prodigy 190 points

below are my observation, correct me if any deviation,

1) CLKMODECLBx = 0, then input is SYSCLK and if =1 then input is AUXPLL

2) if input is SYSCLK, then only EPWMCLKDIV is there in the path to pre scale clock for CLB (Path: from SYSCLK to CLB Clock)

Que:

3) if SYSCLK = 200MHz and EPWMCLKDIV = 0, then can CLB operate at 200MHz? from experiment on CLB counter, it looks like CLB counter can run at even 200MHz (concluded based on count value)

Regards,

+1 Venkata Praneeth Somina 3 months ago in reply to Jay

TI__Intellectual 1160 points

Jay,

Your observations are correct. But 200MHz is more than CLB's recommended maximum frequency.
As mentioned in TRM, maximum frequency is 150MHz for CLB clock. As mentioned in threads TMS320F28379D: CLB working frequency - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums and LAUNCHXL-F28379D: Launchxl-F28379D CLB clock frequency - C2000 microcontrollers forum - C2000︎ microcontrollers - TI E2E support forums, operating CLB at higher frequency is not recommended. This limitation on frequency of CLB is because the tile logic goes through many paths of logic.

Thanks
Praneeth

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TMS320F28388D: CLB clock configuration