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Original question:

TMS320F28379D: Pipeline effects of the CLA

TMS320F28379D: CLA pipeline write-read conflict

Dvir Landwer
Prodigy 160 points
Part Number: TMS320F28379D


Hello,

The question is about the potential write-read conflict in the CLA pipeline.

Is the a write instruction followed immediately by a read instruction could cause potential conflict when using the same floating point register (MRx) or is the conflict only relevant when using the same address (or dependent addresses)?

Consider the following code:

    MMOV16 *MAR0, MR1                           ; Old MR1 should be writen into the 1st address

    MMOVZ16 MR1, @_cla_current21          ; A 2nd (different) address should be loaded into MR1 (new)

 

Is there a conflict here because both instructions use MR1? Is it possible that due to pipeline sequence the new MR1 (with the content of @_cla_current21) will be stored into *MAR0 instead of the old MR1 content?

If indeed there is conflict here, how many intermediate instructions (or MNOPs) should be used to avoid the conflict here? 

 

Thanks

  • 0
    TI__Guru* 93240 points

    Dvir,

    It is the latter scenario.  That is, If you have two instructions, the first writes to memory location A, the second reads from memory location A; according to the pipeline the read happens ahead of the write so you run into this read-before-write hazard. Same with dependent registers. For the C28x, the pipeline will automatically stall the read till the write happens BUT the CLA pipeline will not...so care needs to be taken when writing CLA assembly. 

    However, when writing C code you don't really see these issues / differences.

    3 instructions should separate any such write-read sequence. This is described in the CLA chapter of the TRM.  

    Regards,

    Lori

  • 0 in reply to Lori Heustess
    Prodigy 160 points

    Thank you very much Lori!

    So just to be sure,  if I understand correctly there is no Write-Read conflict/issue in the example I shared where there are two different memory locations but the same floating point register (MR1) in the instructions.

    Code example:

        MMOV16 *MAR0, MR1                           ; Old MR1 should be written into the 1st address

        MMOVZ16 MR1, @_cla_current21          ; A 2nd (different) address should be loaded into MR1 (new)

    Thanks,

    Dvir

  • 0 in reply to Dvir Landwer
    Prodigy 160 points

    Just to clarify, my concern is that new MR1 will be stored into *MAR0 instead of the intended old MR1.

  • 0 in reply to Dvir Landwer
    TI__Guru* 93240 points

    That's correct, Dvir. There is no read/write conflict for the MR1 register.

    Side note: The pipeline conflicts are listed in the TRM in the CLA chapter. Also if it is something the codegen tools can detect, like the MR1 case, it will provide feedback to the user as an error or warning. 

  • 0 in reply to Lori Heustess
    Prodigy 160 points

    Thank you Lori for your helpful support, it is most appreciated.