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Original question:

TMS320F28375S: Setup and Hold specs for GPIO synchronization and the eQEP module

TMS320F28375S: Setup And Hold for GPIO Synchronous Qualification

Zachary Baltzer
Prodigy 30 points

Part Number: TMS320F28375S

I asked a realted question, but fear I may have confused things with bridging a few different topics at once.

My question is, what is the setup and hold requirements for signals going into the GPIO for synchronous qualification?

I have a circuit design where I'd like to know the maximum input speed that a GPIO can be processed in synchronous qualification. In the datasheet, the claim is SYSCLK/2. However, it cannot be exactly SYSCLK/2 due to setup and hold requirements (imagine if the edge of the signal appeared at the same exact time as a rising edge of SYSCLK). This is all assuming the GPIO qualification block in synchronous mode can be thought of like a D flip flop.

  • 0
    TI__Mastermind 33633 points

    Hi Zachary,

    Thanks for your question. Apologies for the delayed response. I am also referring to the previous thread so I am assuming this is still inherently related to using the EQEP.

    While the datasheet doesn’t explicitly state separate setup/hold times for GPIO with qualification, the eQEP’s architecture inherently operates like a clocked logic circuit. This means the signal needs to be stable around the SYSCLK edge.

    Although the general GPIO timing specs (Section 6.9.8.2 of the datasheet) suggest a higher potential frequency, the eQEP module itself is limited to a maximum input frequency of SYSCLK/2. For a 100 MHz SYSCLK, this equates to 50 MHz.

    To ensure reliable operation:

    • Keep your input signal frequency well below 50 MHz.
    • Prioritize clean signal edges.
    • Optimize your PCB layout for signal integrity.
    • Thoroughly test your implementation, gradually increasing the frequency.

    Let me know if you have any further questions.

    Best Regards,

    Zackary Fleenor