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Original question:

TMS320F28P650SH: CMPSS CBC goes wrong

TMS320F28P650DK: CMPSS RAMP clock issue

Alice
Expert 5305 points

Part Number: TMS320F28P650DK

Hello,
    Greeting for the day!
    There is customer's issue, could you help to clarify? Thank you so much.

     The prescale setting was set successful.

      Regarding my actual tests, RAMPxSTS performs subtraction according to RAMPxCLK, while RAMPxDLYA performs subtraction according to SYSCLK.

     In the TRM images, both RAMPxSTS and RAMPxDLYA perform subtraction according to RAMPxCLK.

     My SYSCLK is 200MHz, and after frequency division configuration, RAMPxCLK is 100MHz.

     During verification, I found that RAMPxSTS performs subtraction according to 100MHz, whereas RAMPxDLYA still performs subtraction according to 200MHz, which does not match the annotations in the manual images.

     

  • 0
    TI__Expert 7520 points

    Hello,

    The ramp delay is defined in system clock cycles after a PWMSYNC event, while the ramp clock divider is used to derive the ramp generator clock from SYSCLK. So, your observation will be consistent with that behavior.

    Best Regards,

    Masoud