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Original question:

TMS320F28P550SG: [FAQ]: F28P550 ADC external reference configuration in sysconfig

TMS320F28P550SJ: AI arc detection

Chi Zhang2
Intellectual 2990 points

Part Number: TMS320F28P550SJ

Hi Expert, 

 

My customer is using F28P55 for AI Arc detection. and there are some questions here. please help to share some advice. 

 

1.Could you clarify the differences between the provided projects and recommend which one is suitable for our board? Should we use the same dataset for both data collection and inference, or are two separate sets required?

The projects we currently have include: arc_fault_detection_f28p55x_npu , F28P55X_AR_X_demo , and arc_fault_detection_f28p55x_npu_card .

The official Arc Fault project is available in C2000 Digital Power SDK in the below path.
’{C2000_DP_SDK_PATH}\solutions\tida_010955‘

Different data should be used for training and real-time inference , otherwise you won’t be able to evaluate trained ML model reliably . But both of these must be originated from same system.

 

Please confirm that the ARC program is the one shown below.

 

2 What is the abbreviation for BNORM, and what does it mean?

 

3 For AFCI detection, are there any recommended configurations for the convolution layer?

 

4 For AFCI detection,How many data points need to be collected for training at TI Edge AI Studio?

 

5 What does AFE mean?

 

 

6 “Live DC arc fault detection test: Achieve >98% detection accuracy at UL 1699B test conditions. ”What does "Achieve >98%" mean? Does it mean that out of 100 arcing events detected, 98 are genuine arcing events? Or does it mean that out of every 100 arcing events that occur, 98 can be detected?

 

7 Do we need to perform FFT processing on the 1024 consecutive current samples here? What does “magnitude” do? What does “Feature Select” do?

 

8 Should we exclude noise frequencies, such as the power supply's switching frequency, here? What preprocessing is needed for the acquired signal?

 

9 What does "feaures" mean here?

 

BR

Chi

  • 0
    TI__Prodigy 210 points

    Hi Chi,

    Amir Hussain is the design owner for this. He will be the best person to comment on your questions.

    Thanks & regards,

    Shamik

  • 0
    TI__Expert 5515 points

    Hi Chi

    Please find my response below:

    1. The software that you downloaded from SDK is the latest and the best version, both for data collection and inference. This software is based on F28P55 control card. The same software is compatible with Edge AI studio for data collection and seeing the inference result on Edge AI studio. You should use different dataset for inference. The system has be same. This means you can perform the inference on the same system where the data is collected as the model training is system dependent. I will also suggest to read carefully the software/user guide downloaded from the SDK.

    2. Can you tell where did you come across BNORM?

    3. I will request model expert to comment on this?

    4. You typically need 2s of normal and arc data each for each operating point (eg. 400V, 8A). 2s of data implies 500k samples at 250kHz sampling rate.

    5. AFE implied analog front end board.

    6. Please see this post: 

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1637068/tms320f28p550sj-what-does-98-in-afci-mean/6311831?tisearch=e2e-sitesearch&keymatch=%20user%3A531160#

    7.Please go through tida_010955_sw. These details are provided there.

    8. You should not exclude noise frequency. 

    9. Features are the parameters that are input to the model after the FFT are preprocessed. For detail, please go through tida_010955_sw.

    Thank you 

    Amir Hussain

  • 0 in reply to Amir Hussain
    TI__Expert 5515 points

    Hi Chi

    The best person to answer Q.3 is on vacation until April 29. Please expect a response after this date.

    Thank you 

    Amir Hussain

  • 0
    TI__Prodigy 510 points

    Hi Chi, Regarding Question 3,

    There is no recommended configurations for the convolution layer for AFCI. Convolution layer configuration are less dependent on the model application.

    What would rather be the perspective is that, we need to make sure that the convolution layer can run best on the hardware accelerator. And for that, it is usually recommended for the channels to be multiples of 4 & also that the input features are in powers of 2. In this way, the hardware accelerator (TinyEngine NPU) is seldom left unused, which means maximum bang on the buck for power & latency.

    Also, in the same context, depth of convolution layers is a good topic to think about. The more the layers, the better the feature extraction capability, but also means more computing complexity and higher latency. Also, more channels in the intermediate layers mean more rich extraction of information, so better AI capability