• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 82 subscribers
  • Views 136 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

F29H85X-SOM-EVM: Not able to load Ram based HSM run time.

F29H850TU: Unable to Load HSM RAM Image during Code Provisioning through UART

Marek Kowalczyk
Prodigy 30 points

Part Number: F29H850TU
Other Parts Discussed in Thread: LAUNCHXL-F29H85X

Hello,

I have run into an issue during my first attempt to perform Code Provisioning on LAUNCHXL-F29H85X. I have performed Key Provisioning with a successful result. Now I try to perform Code Provisioning but as soon as I select "3-Load HSM RAM Image" in uart_flash_programmer, the device stops responding. I am uploading tifs_f29h85x_hs_se_code_provisioning.release.hs.hsmimage built using an unmodified makefile. 

I have added some logs on secondary UART into ram_based_sbl and have found out that execution never returns from this place in code (it DOES NOT return any status and DOES NOT go into Example_Error()):

In file: sbl_key_provisioning.c
In function: int32_t loadHSMRT(uint32_t BaseAddress)
Line: hsmStatus = HsmClient_waitForBootNotify(NULL, 0);

So currently I'm stuck with cannot proceed with Code Provisioning. I am following instructions from docs file in TIFS.

Package versions: f29h85x-sdk_1_03_00_00, tifs_f29h85x_01_03_00_00, otp_keywriter_f29h85x_SR_10_1_03_00_00.

Silicon version info (text on the uC): 3LA-54A449W

I am using development keys provided in the TI packages.

Information about my device from uart_flash_programmer:

uart_flash_programmer

I'm using command: uart_flash_programmer.exe --device f29h85x --port COM17 --kernel ram_based_uart_sbl.bin --hsmrt tifs_f29h85x_hs_se_code_provisioning.Release.hs.hsmimage --cpseccfg seccfg.bin

Received packet with SoC ID content, printing the info...

----------------------------
SoC ID HW Info:
----------------------------
Part ID            : 0x1706
Part number        : 0xff
PG version         : 0
ROM version        : 0
Metal version      : 0
----------------------------
SoC ID CPU Info:
----------------------------
C29 BootROM version: 0x10000
----------------------------
SoC ID HSM Public Info:
----------------------------
Device name        : F29H85X
Device type        : HS_KP (Key Provisioned)
HSM BootROM version: 0x10000
----------------------------
SoC ID HSM Secure Info:
----------------------------
Is prime device    : true
# keys provisioned : 2
Key revision       : SMPK (Secondary Manufacturer Key)  (HS-SE only)
SW SBL revision    : 0
SW HSMRt revision  : 0
SW SSU revision    : 0
SW FLW revision    : 0
TI MPK hash        : ea0a5e7e2acbf7b587821766454242f87a23ca45cc1ad0d595661468eb571558b019a4cd88ac5c2e901ce8ca171c2dceed66273e8796c839597402eff5c32ccf
Active MPK hash    : ce0c44734447afec12ba0b2226c3bdbc15576d212323ece46a9c4ccd6a463e417086083fee572a09a9496dbed447a9f13f9cf535fad75b18e0ee095a4e783c62
Device UID         : a0390a292a738f32f04f8c11c46f303604ef72dd741a42d981ad6877cdde83858de18edd8f4b2ab63725c9e6ff3b647688579555983811894f2fc72867a8b53d
----------------------------

Received packet with Boot ROM Status, printing the info...

----------------------------
Boot ROM Checks:
----------------------------
(Omitting Passed or Ignored Boot Flow Execution Status)
No Failed Steps
----------------------------
SSU Checks:
----------------------------
(Omitting Passed or Ignored Boot Flow Execution Status)
No Failed Steps
----------------------------
Boot ROM Status:
----------------------------
Link 0 Elasped Cycle: 3068757
Reset Count         : 260107919
Reset Cause (RESC)  : Reset by XRSn,Reset by NMI Watchdog (NMIWDRSn), XRSn_pin ON, Debugger Disconnected (0x4000000a)
System Clock        : 200 MHz
ECC DR1 Error Addr  : 0
ECC DR2 Error Addr  : 0
Boot Mode           : UART Boot (1)
Bootloader Lock     : Disabled
Life Cycle State    : HS_KP
Link 0 Error ID     : No Error
----------------------------
SSU Status:
----------------------------
CPU1 Active Bank Mgmt Addr: 0xdeadcafe
CPU3 Active Bank Mgmt Addr: 0xdeadcafe
CPU1 Active Sec Cfg Addr  : 0xdeadcafe
CPU3 Active Sec Cfg Addr  : 0xdeadcafe
Bank Mode      : Bank Mode 0
CPU1 Bank Swap : Default Swap
CPU3 Bank Swap : Default Swap
CPU1 Sec Cfg   : Default Active
CPU3 Sec Cfg   : Default Active
SSU Mode       : SSU Mode 1
----------------------------
NMI Status:
----------------------------
ESM Raw Status : 0
EA CPU1 PR  : (Err Type)0, (High-Pri Addr)0xdeadcafe, (Low-Pri Addr)0xdeadcafe, (PC Addr)0xdeadcafe
EA CPU1 DR1 : (Err Type)0, (High-Pri Addr)0xdeadcafe, (Low-Pri Addr)0xdeadcafe, (PC Addr)0xdeadcafe
EA CPU1 DR2 : (Err Type)0, (High-Pri Addr)0xdeadcafe, (Low-Pri Addr)0xdeadcafe, (PC Addr)0xdeadcafe
EA CPU1 DW  : (Err Type)0, (High-Pri Addr)0xdeadcafe, (Low-Pri Addr)0xdeadcafe, (PC Addr)0xdeadcafe
EA CPU1 Int : (Err Type)0, (High-Pri Addr)0xdeadcafe, (Low-Pri Addr)0xdeadcafe, (PC Addr)0xdeadcafe
----------------------------

  • 0
    TI__Intellectual 1680 points

    Hi Marek,

    Could you check the following things once:

    1. The CP binary has been built in the Release Configuration with CONFIG=RAM.
    2. The CP binary is built using the same algorithm as the keys used.
    3. The RAM Based UART SBL is built in SECURE KP and CP or SECURE ONLY CP Build Configuration.
    4. The RAM Based UART SBL is built using the same algorithm as the keys used.

    Thanks and Regards,
    Aditya Singal

  • 0 in reply to Aditya Singal
    Prodigy 30 points

    Hello Aditya,

    1. The binaries have been built using commands attached below. For CP binary CONFIG=RAM was used. I'm not sure Debug/Release configuration, since I've used make command and not the CCS build.
    2. I'm using DEVICE_TYPE=HS and ALGORITHM=RSA4k which corresponds to tifs/tools/boot/signing/mcu_custMpk.pem for CP binary signing. For KP I've used keys_devel/rsa4k/smpk.pem from Keywriter which contains exactly the same key.
    3. The RAM Based UART SBL was built in     SECURE_KP_CP Build Configuration - using APP=SECURE parameter in make command
    4. Yes - same as in point 2.

    cd ~/ti/tifs_f29h85x_01_03_00_00
make -s -C ~/ti/tifs_f29h85x_01_03_00_00/hsm_firmware/f29h85x/code_provisioning/hsm0-0_nortos/ti-arm-clang DEVICE=f29h85x DEVICE_TYPE=HS DBG_ENABLED=no ENC_ENABLED=yes CONFIG=RAM ALGORITHM=RSA4k all

cd ~/ti/f29h85x-sdk_1_03_00_00/
cd examples/driverlib/single_core/flash/ram_based_sbl/ccs/
make -s -C ~/ti/f29h85x-sdk_1_03_00_00/examples/driverlib/single_core/flash/ram_based_sbl/ccs -f ram_based_uart_sbl.mk all APP=SECURE ALGORITHM=RSA4k

/usr/bin/python3 ~/ti/f29h85x-sdk_1_03_00_00/tools/misc/genSeccfgBin.py ~/ti/ccs2040/ccs/tools/compiler/ti-cgt-c29_2.0.0.STS/bin/c29objcopy ~/ti/f29h85x-sdk_1_03_00_00/source/defseccfgbin/default_seccfg_bankmode_0_ssumode1.out ~/ti/f29h85x-sdk_1_03_00_00/tools/boot/signing/mcu_rom_image_gen.py ~/ti/smpk.pem /usr/bin/python3

./uart_flash_programmer --device f29h85x --port /dev/ttyACM0 --kernel ram_based_uart_sbl.bin --hsmrt tifs_f29h85x_hs_se_code_provisioning.release.hs.hsmimage --cpseccfg seccfg.bin

  • 0 in reply to Marek Kowalczyk
    TI__Intellectual 1680 points

    Hi Marek,

    Did you give the board a Power On Reset after Key Provisioning?

    Thanks and Regards,
    Aditya Singal