TMS320F28P650DK: CLB.HLC feature in pipeline mode

LIU LIU

Hi TI support team,

From this topic https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1119213/tms320f280025c-what-s-the-clb-pipeline-mode?keyMatch=CLB%20pipeline&tisearch=universal_search

You said in the pipeline mode, it allows the HLC events to use a CLB output from the previous cycle.

My question:

What does the CLB output include? Is it OUTPUTLUT0‑7 and AOC.BOUNDARY OUT0‑7?
However, from Figure 8‑19 in the TRM of the TMS320F28P65x, it appears that AOC.BOUNDARY OUT0‑7 are delayed by one cycle before being fed to the HLC. If the CLB output includes AOC.BOUNDARY OUT0‑7, does that mean that in pipeline mode, AOC.BOUNDARY OUT0‑7 will be delayed by one additional cycle? Or does "CLB output" refer only to OUTPUTLUT0‑7?

2 days ago

0 Venkata Praneeth Somina 2 days ago

TI__Intellectual 2080 points

Hi Liu,
I will get back to you on Monday.
Thanks
Praneeth

0 Venkata Praneeth Somina 9 hours ago in reply to Venkata Praneeth Somina

TI__Intellectual 2080 points

Hi Liu,
When, CLB pipeline mode is enabled, the operations of the HLC and Counter modules are changed.
The pipeline mode causes the pipelined versions of outputs are delayed by 1 clock cycle to be used as the source of the HLC. So in pipelined version, the reason for the delay is different from when the pipeline is not enabled. So only one clock cycle delay will be obsserved.
Thanks
Praneeth

0 LIU LIU 6 hours ago in reply to Venkata Praneeth Somina

Intellectual 410 points

Hi Venkata,

Please refer to Figure 8‑19 in the TRM. What is the meaning of OUT0-7(start form AOC) delayed by one cycle?

Does it mean that OUT0-7(start form AOC) is only delayed by one cycle when pipeline mode is enabled, or is it delayed by one cycle regardless of whether pipeline mode is enabled?

0 Venkata Praneeth Somina 55 minutes ago in reply to LIU LIU

TI__Intellectual 2080 points

Hi Liu,
As mentioned in the technical reference manual, outputs are pipelined. So in both cases, pipeline mode enabled and disabled, the outputs are treated differently. In both the cases, delay will be one cycle.
Thanks
Praneeth

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TMS320F28P650DK: CLB.HLC feature in pipeline mode