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Original question:

TMS320F280025C: what's the CLB PIPELINE mode?

TMS320F28P650DK: CLB.HLC feature in pipeline mode

LIU LIU
Intellectual 410 points

Part Number: TMS320F28P650DK

Hi TI support team,

From this topic https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1119213/tms320f280025c-what-s-the-clb-pipeline-mode?keyMatch=CLB%20pipeline&tisearch=universal_search

You said in the pipeline mode, it allows the HLC events to use a CLB output from the previous cycle.

My question: 

  1. What does the CLB output include? Is it OUTPUTLUT0‑7 and AOC.BOUNDARY OUT0‑7?
  2. However, from Figure 8‑19 in the TRM of the TMS320F28P65x, it appears that AOC.BOUNDARY OUT0‑7 are delayed by one cycle before being fed to the HLC. If the CLB output includes AOC.BOUNDARY OUT0‑7, does that mean that in pipeline mode, AOC.BOUNDARY OUT0‑7 will be delayed by one additional cycle? Or does "CLB output" refer only to OUTPUTLUT0‑7?
  • 0
    TI__Expert 3130 points

    Hi Liu, 
    I will get back to you on Monday.
    Thanks
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    TI__Expert 3130 points

    Hi Liu,
    When, CLB pipeline mode is enabled, the operations of the HLC and Counter modules are changed.
    The pipeline mode causes the pipelined versions of outputs are delayed by 1 clock cycle to be used as the source of the HLC. So in pipelined version, the reason for the delay is different from when the pipeline is not enabled. So only one clock cycle delay will be obsserved.
    Thanks
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    Intellectual 410 points

    Hi Venkata,

    Please refer to  Figure 8‑19 in the TRM. What is the meaning of  OUT0-7(start form AOC) delayed by one cycle?

    Does it mean that  OUT0-7(start form AOC) is only delayed by one cycle when pipeline mode is enabled, or is it delayed by one cycle regardless of whether pipeline mode is enabled?

  • 0 in reply to LIU LIU
    TI__Expert 3130 points

    Hi Liu,
    As mentioned in the technical reference manual, outputs are pipelined. So in both cases, pipeline mode enabled and disabled, the outputs are treated differently. In both the cases, delay will be one cycle.
    Thanks 
    Praneeth

  • 0 in reply to Venkata Praneeth Somina
    Intellectual 410 points

    Hi  Venkata,

    I still not understand. Let's take an example:

    Based on table 8-13, I can choose a trigger for HLC.

    1. when I choose CLB_OUT_0 as HLC trriger. In pipeline mode and non‑pipeline mode, how many clock cycles is the delay in each case?

    2. Based on Figure 8-18， I can set CLB_OUTPUT_COND_CTRL_0.AYSNC_COND_EN=0. So that CLB_OUT_0 can bypass to CLB_ASYNC_OUT_0. Then I choose CLB_ASYNC_OUT_0 as HLC trriger. In pipeline mode and non‑pipeline mode, how many clock cycles is the delay in each case? Is there any different with CLB_OUT_0?

    If in all cases, delay will be one cycle. What's the meaning of pipeline mode?

  • +1 in reply to LIU LIU
    TI__Expert 3130 points

    Hi Liu,
    Cell output is delayed by one cycle in pipeline mode. It is not the output before AOC. What ever that comes at the output of CLB cell will be delayed by 1 cycle in pipeline mode. If you are using AOC, internal delay can still be there. 
    1. In pipe line mode it will be deterministically 1 cycle delay
    2. Here there will be delay becasue of AOC, the delay will be more than 1 cycle.
    Thanks 
    Praneeth