Urgent: Mapping CLA data RAM to CLA space

Frank H Zhang

Other Parts Discussed in Thread: TMS320F28035, CONTROLSUITE

Hi,

I am using TMS320F28035.

So far, I have CLA ISR and Epwm_ISR. The CLA ISR is triggered by Epwm at timebase=0.

I am now trying to use CLAsine function from CLAmath library. According to the CLAsine example from ControlSUITE, I have mapped the CLA data RAM to CLA space, like this:

Cla1Regs.MMEMCFG.bit.RAM1E = 1;

But whenever I enabled the data RAM mapping as above, the Epwm_ISR (in CPU) stopped working. The CLAsine function worked fine.

If I disabled the data RAM mapping, like

Cla1Regs.MMEMCFG.bit.RAM1E = 0;

Then, the Epwm_ISR became fine, but the CLAsine function stopped working.

I don't know why the CLA data RAM mapping blocks the Epwm_ISR ?

I really hope someone can help me with this.

Thank you.

over 13 years ago

0 Frank H Zhang over 13 years ago

Expert 1515 points

Hi,

I just want to mention a few things here:

1. The linker file that I am using is from the ClaAdc example in ControlSUITE, but I added command

CLAmathTables : > RAML2, PAGE = 1

2. I included the following files in my project:

CLAmath_type0.h

CLAmathLib_type0.inc

CLAsincosTable_type0.asm

3. In the assembly file, CLA.asm,

I pretty much just copied the code from the CLA_sine example's assembly code.

Thank you.

0 Lori Heustess over 13 years ago in reply to Frank H Zhang

TI__Guru* 90965 points

Is there something else that is mapped to RAML2?

0 Frank H Zhang over 13 years ago in reply to Lori Heustess

Expert 1515 points

Here is what the linker command file looks like:

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN                : origin = 0x000000, length = 0x000002
   RAMM0                : origin = 0x000050, length = 0x0003B0
   RAML0L1              : origin = 0x008000, length = 0x000C00
   RAML3                : origin = 0x009000, length = 0x001000
   RESET                : origin = 0x3FFFC0, length = 0x000002
   IQTABLES             : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2            : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3            : origin = 0x3FEBDC, length = 0x0000AA   /* IQ Math Tables in Boot ROM */

   BOOTROM              : origin = 0x3FF27C, length = 0x000D44

PAGE 1 :

   BOOT_RSVD            : origin = 0x000002, length = 0x00004E     /* Part of M0, BOOT rom will use this for stack */
   RAMM1                : origin = 0x000480, length = 0x000380     /* on-chip RAM block M1 */
   RAML2                : origin = 0x008C00, length = 0x000400
   CLA1_MSGRAMLOW       : origin = 0x001480, length = 0x000080
   CLA1_MSGRAMHIGH      : origin = 0x001500, length = 0x000080
}

SECTIONS
{
   /* Setup for "boot to SARAM" mode:
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code. */
   codestart        : > BEGIN,     PAGE = 0
   ramfuncs         : > RAMM0      PAGE = 0
   .text            : > RAML0L1,   PAGE = 0
   .cinit           : > RAMM0,     PAGE = 0
   .pinit           : > RAMM0,     PAGE = 0
   .switch          : > RAMM0,     PAGE = 0
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   .stack           : > RAMM1,     PAGE = 1
   .ebss            : > RAML2,     PAGE = 1
   .econst          : > RAML2,     PAGE = 1
   .esysmem         : > RAML2,     PAGE = 1

   CLAmathTables    : > RAML2,     PAGE = 1

   IQmath           : > RAML0L1,   PAGE = 0
   IQmathTables     : > IQTABLES, PAGE = 0, TYPE = NOLOAD

   Cla1Prog         : LOAD = RAML0L1,
                      RUN = RAML3,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      PAGE = 0

   Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW,   PAGE = 1
   CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
}

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

I also want to mention that I have been using TMS320F28035 for a little while, but when it comes to CLA or dealing with memory structure, linker and mapping, I am really a beginner. So any suggestions on how I can solve this problem or on what reference/ learning material I should look into are appreciated.

Thank you,

Frank

0 Vishal_Coelho over 13 years ago in reply to Frank H Zhang

TI__Mastermind 20850 points

Frank,

If you plan on having the CLA use RAML2 you need the move the other stuff to a different block. i.e ebss, econst and esysmem

Frank H Zhang said:
.stack           : > RAMM1,     PAGE = 1
   .ebss            : > RAML2,     PAGE = 1
   .econst          : > RAML2,     PAGE = 1
   .esysmem         : > RAML2,     PAGE = 1

   CLAmathTables    : > RAML2,     PAGE = 1

Once you transfer over control of the RAM block to the CLA through RAM1E bit, the CLA has control of the RAML2 so if your EPWM isr is trying to access something in the ebss section it gets locked out and reads 0s. similarly if you set RAM1E to 0 the CPU has control and your CLAsine routine cant access the math tables in RAML2

0 Frank H Zhang over 13 years ago in reply to Vishal_Coelho

Expert 1515 points

Hi Vishal,

It is working now, but I still have two more questions.

Firstly,

as you pointed out above, I looked for an alternative location for .ebss , .econst, .esysmem, and I did this (shown below) , but it didn't work

   .ebss            : > RAML3,     PAGE = 0
   .econst          : > RAML3,     PAGE = 0
   .esysmem         : > RAML3,     PAGE = 0

So, I thought RAML3 might be full, so let me try another location RAML0L1, and it worked.

I am not sure if I was right about " RAML3 might be full" or there were some restrictions?

Secondly, if I want to have a good /complete understanding about the memory mapping rules, which TI documents or reference should I read?

Thank you very much,

Frank

0 Vishal_Coelho over 13 years ago in reply to Frank H Zhang

TI__Mastermind 20850 points

RAML3 is the program space for the CLA. The entire block is mapped over to the CLA and all the tasks run out of this block. You cant have any C28x sections in RAML3 once you map it over to the CLA, the C28 is essentially locked out of this block.

The CLA user guide, for whichever device you are using, talks about this specifically but for a general treatment on memory sections you will want to take a look at

1. Assembler UG SPRU513D

2. Compiler UG SPRU514D

0 Frank H Zhang over 13 years ago in reply to Vishal_Coelho

Expert 1515 points

Hi Vishal,

Thank you very much for your help.

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Urgent: Mapping CLA data RAM to CLA space