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Hello.
I am using two F2811 DSPs configured to transfer data via McBSP configured as SPI, one F2811 DSP is configured as McBSP as
SPI master and the other F2811 DSP is configured as McBSP slave device.
PROBLEM: The master McBSP set as SPI is configured to xmit known data pattern of 0xAA and the data coming out of SPI master is correct value of 0xAA
and is verified on a scope. See file McBSP Master.png. However, the slave McBSP configured as SPI seems to get incorrect data 0x54 or 0x00 in the
receive buffer.The F2811 slave DSP's SPI port is used to transfer data from slave device to external processor via SPI port. See file SLAVE DSP SPI data out.png
The attached documents show data coming out of McBSP as SPI(master) as 0xAA and the second document shows data coming out of
F2811 slave device SPI port to be 0x54. The upper most significant bit is lost or incorrect.
Also attached is screen shots of McBSP and SPI registers content on SLAVE DSP before error and after error.
*************************************************************************************
Following signals are connected from McBSP SPI master to McBSP SPI slave.
*************************************************************************************
MASTER: CLKXA(23), FSXA(22), SDXA (19), MDXA(18)
SLAVE: CLKXA(23), FSXA(22), MDXA(18), SDXA(19)
*************************************************************************************
CLOCK setup:
*************************************************************************************
SYSCLOCK: 120MHz
HISPCLK: 120MHz.
LSPCLK: 30MHz.
CLKG= 30MHz/ (11+1) =2.5MHz.
*************************************************************************************
McBSP as SPI Master Register setup:
*************************************************************************************
EALLOW;
// Configure McBSP as SPI as MASTER.
McbspaRegs.SPCR2.all=0x0000;
McbspaRegs.SPCR1.all=0x0000;
//step2. setup as SPI master
McbspaRegs.SPCR1.bit.CLKSTP = 0x2; //clock stop mode,
//high inactive state without delay
McbspaRegs.PCR.bit.CLKXP = 0x0;
McbspaRegs.PCR.bit.CLKRP = 0x0;
McbspaRegs.XCR2.bit.XPHASE = 0x0; //single phase transmit frame
McbspaRegs.RCR2.bit.RPHASE = 0x0; //single phase receive frmae
McbspaRegs.XCR1.bit.XFRLEN1 = 0x0; //transmit frame length 1 word
McbspaRegs.RCR1.bit.RFRLEN1 = 0x0; //receive frame length 1 word
McbspaRegs.XCR1.bit.XWDLEN1 = 0x0; //0x2; //transmit word length 16
McbspaRegs.RCR1.bit.RWDLEN1 = 0x0; //0x2; //receive word length 16
McbspaRegs.PCR.bit.CLKXM = 0x1; //It's SPI master!!
McbspaRegs.PCR.bit.SCLKME = 0x0; //clock by CLKG is derived from CPU clock
McbspaRegs.SRGR2.bit.CLKSM = 0x1;
McbspaRegs.SRGR1.bit.CLKGDV = 0xb; // divide CLKG by 16
McbspaRegs.PCR.bit.FSXM = 0x1; //The MFSXA pin is output driven by FSGM bit
McbspaRegs.SRGR2.bit.FSGM = 0x0; //drive frame sync pulse on MFSXA pin
McbspaRegs.PCR.bit.FSXP = 0x1; //MFSXA pin is active low
McbspaRegs.XCR2.bit.XDATDLY = 0x1;
McbspaRegs.RCR2.bit.RDATDLY = 0x1;
//step3. enable sample rate generator
McbspaRegs.SPCR2.bit.GRST = 0x1;
//delay_loop(); //wait for McBSP logic to stabilize
McbspaRegs.MFFTX.all=0x0000;
McbspaRegs.MFFRX.all=0x001F;
McbspaRegs.MFFCT.all=0x0;
McbspaRegs.MFFINT.all=0x0;
McbspaRegs.MFFST.all=0x0;
McbspaRegs.MFFTX.bit.MFFENA=1; // Enable FIFO
McbspaRegs.MFFTX.bit.TXFIFO_RESET=1; // Enable Transmit channel
McbspaRegs.MFFRX.bit.RXFIFO_RESET=1; // Enable Receive channel
clkg_delay_loop(); // Wait at least 2 SRG clock cycles->>100
//step5. enable transmitter
McbspaRegs.SPCR2.bit.XRST = 1; //enable the transmitter
McbspaRegs.SPCR1.bit.RRST = 1; //enable the receiver
McbspaRegs.SPCR2.bit.FRST = 0x1; //SPI master, internally generated frame sync
EDIS;
*************************************************************************************
McBSP as SPI Master Register setup:
*************************************************************************************
EALLOW;
McbspaRegs.SPCR2.all=0x0000;
McbspaRegs.SPCR1.all=0x0000;
//step2. setup as SPI slave
McbspaRegs.SPCR1.bit.CLKSTP = 0x2; //clock stop mode,
//high inactive state without delay
McbspaRegs.PCR.bit.CLKXP = 0x0;
McbspaRegs.PCR.bit.CLKRP = 0x0;
McbspaRegs.XCR2.bit.XPHASE = 0x0; //single phase transmit frame
McbspaRegs.RCR2.bit.RPHASE = 0x0; //single phase receive frame
McbspaRegs.XCR1.bit.XFRLEN1 = 0x0; //transmit frame length 1 word
McbspaRegs.RCR1.bit.RFRLEN1 = 0x0; //receive frame length 1 word
McbspaRegs.XCR1.bit.XWDLEN1 = 0x0; //0x2; //transmit word length 16
McbspaRegs.RCR1.bit.RWDLEN1 = 0x0; //0x2; //receive word length 16
McbspaRegs.PCR.bit.CLKXM = 0x0; //It's SPI slave!!
McbspaRegs.PCR.bit.SCLKME = 0x0; //clock by CLKG is derived from CPU clock
McbspaRegs.SRGR2.bit.CLKSM = 0x1;
McbspaRegs.SRGR1.bit.CLKGDV = 0x1; //
McbspaRegs.PCR.bit.FSXM = 0x0; //The MFSXA pin is input
//McbspaRegs.SRGR2.bit = 0x0; //drive frame sync pulse on MFSXA pin
McbspaRegs.PCR.bit.FSXP = 0x1; //MFSXA pin is active low
McbspaRegs.XCR2.bit.XDATDLY = 0x0;
McbspaRegs.RCR2.bit.RDATDLY = 0x0;
//step3. enable sample rate generator
McbspaRegs.SPCR2.bit.GRST = 0x1;
//delay_loop(); //wait for McBSP logic to stabilize
//step4. initialize FIFO for receiver
McbspaRegs.MFFTX.all=0x0000;
McbspaRegs.MFFRX.all=0x001F;
McbspaRegs.MFFCT.all=0x0;
McbspaRegs.MFFINT.all=0x0;
McbspaRegs.MFFST.all=0x0;
McbspaRegs.MFFTX.bit.MFFENA=1; // Enable FIFO
McbspaRegs.MFFTX.bit.TXFIFO_RESET=1; // Enable Transmit channel
McbspaRegs.MFFRX.bit.RXFIFO_RESET=1; // Enable Receive channel
clkg_delay_loop(); // Wait at least 2 SRG clock cycles->>100
//step5. enable transmitter
McbspaRegs.SPCR2.bit.XRST = 1; //enable the transmitter
McbspaRegs.SPCR1.bit.RRST = 1; //enable the receiver
EDIS;
*************************************************************************************
// spi init
*************************************************************************************
void spi_init()
{
SpiaRegs.SPICCR.all =0x0008;
SpiaRegs.SPICTL.all =0x0006;
SpiaRegs.SPIBRR =0x0004; // LSPCLK = 2, SYSCLK/4
// = 120/2*LSPCLK = 30Mhz
// SPICLK = 30 /SPIBBR+1
// = 30 /(4+1)
// = 7.5 Mhz
// Relinquish SPI from Reset
SpiaRegs.SPICCR.all =0x0098;
// Set so breakpoints don't disturb xmission
SpiaRegs.SPIPRI.bit.FREE = 1;
//initialize SPI FIFO
SpiaRegs.SPIFFTX.all=0xE040;
SpiaRegs.SPIFFCT.all=0x02;
SpiaRegs.SPIFFTX.all=0xE040;// Tx fifo reset
// Enable Enhanced Tx fifo
// Enable Tx fifo operation
// Tx fifo interrupt clear
// Tx fifo interrupt levels = 0
SpiaRegs.SPIFFRX.all=0x204f;// Enable Rx fifo operation
// Rx fifo interrupt clear
// Rx fifo interrupt levels = 0xf
// Zero delay between every transfer from FIFO xmt buffer to transmit shift register.
SpiaRegs.SPIFFCT.all=0x0; // Tx fifo delay = 0
}
