TMS320F28379D: MCBSP SPI More than 32 Bits Slave Receive

Varun Malladi

Intellectual 270 points

Part Number: TMS320F28379D

Hello there,

I am doing a McBSP channel B as slave and trying to read the data sent by master. This is the master data

uint16 TG0_TX_DATA[8] = {0xF0F0, 0xF111, 0x0023, 0x1000, 0xFF00, 0x1111}

And this is what I am receiving, sometimes jumbling here and there.

First of all is it advisable to do more than 32 bits on one stretch using McBSP? Is it doable ? What can I do to read it correctly?

McBSP is bit confusing, any help would be appreciated. I have attached my configuration of McBSP channel, and the master SPI signal. Can you let me know why I get jumbled?

McBspInit.c

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void initSPImode()
{
    //
    // Reset FS generator, sample rate generator, transmitter, receiver.
    //
    McBSP_resetFrameSyncLogic(MCBSPB_BASE);
    McBSP_resetSampleRateGenerator(MCBSPB_BASE);
    McBSP_resetTransmitter(MCBSPB_BASE);
    McBSP_resetReceiver(MCBSPB_BASE);
    //
    // Set Rx sign-extension and justification mode.
    //
    McBSP_setRxSignExtension(MCBSPB_BASE, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);
    //
    // Enable DLB mode. Comment out for non-DLB mode.
    //
   // McBSP_enableLoopback(MCBSPB_BASE);
    //
    // Enable clock stop mode.
    //
    McBSP_setClockStopMode(MCBSPB_BASE, MCBSP_CLOCK_SPI_MODE_NO_DELAY);
    //
    // Set Rx & Tx delay to 1 cycle.
    //
    McBSP_setRxDataDelayBits(MCBSPB_BASE, MCBSP_DATA_DELAY_BIT_0);
    McBSP_setTxDataDelayBits(MCBSPB_BASE, MCBSP_DATA_DELAY_BIT_0);
    //
    // Set CLKX & FSX source as sample rate generator.
    //
    McBSP_setTxClockSource(MCBSPB_BASE, MCBSP_EXTERNAL_TX_CLOCK_SOURCE);
    McBSP_setRxClockSource(MCBSPB_BASE, MCBSP_INTERNAL_RX_CLOCK_SOURCE);
    McBSP_setTxFrameSyncSource(MCBSPB_BASE, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE);
    McBSP_setRxFrameSyncSource(MCBSPB_BASE, MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE);
    //
    // Set Tx and Rx clock and frame-sync polarity.
    //
    McBSP_setTxFrameSyncPolarity(MCBSPB_BASE, MCBSP_TX_FRAME_SYNC_POLARITY_LOW);
    McBSP_setTxClockPolarity(MCBSPB_BASE, MCBSP_TX_POLARITY_FALLING_EDGE);
    McBSP_setRxClockPolarity(MCBSPB_BASE, MCBSP_RX_POLARITY_RISING_EDGE);
    //
    // Initialize McBSP data length.
    //
    McBSP_setRxDataSize(MCBSPB_BASE, MCBSP_PHASE_ONE_FRAME,
                        MCBSP_BITS_PER_WORD_16, 5);
    McBSP_setTxDataSize(MCBSPB_BASE, MCBSP_PHASE_ONE_FRAME,
                        MCBSP_BITS_PER_WORD_16, 5);
    //
    // Set frame synchronization pulse period to 1 CLKG cycle.
    //
    McBSP_setFrameSyncPulsePeriod(MCBSPB_BASE, 0);
    //
    // Set frame-sync pulse width to 1 CLKG cycle.
    //
    McBSP_setFrameSyncPulseWidthDivider(MCBSPB_BASE, 0);
    //
    // Set the trigger source for internally generated frame-sync pulse.
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

void initSPImode()
{
    //
    // Reset FS generator, sample rate generator, transmitter, receiver.
    //
    McBSP_resetFrameSyncLogic(MCBSPB_BASE);
    McBSP_resetSampleRateGenerator(MCBSPB_BASE);
    McBSP_resetTransmitter(MCBSPB_BASE);
    McBSP_resetReceiver(MCBSPB_BASE);

    //
    // Set Rx sign-extension and justification mode.
    //

    McBSP_setRxSignExtension(MCBSPB_BASE, MCBSP_RIGHT_JUSTIFY_FILL_ZERO);

    //
    // Enable DLB mode. Comment out for non-DLB mode.
    //
   // McBSP_enableLoopback(MCBSPB_BASE);

    //
    // Enable clock stop mode.
    //
    McBSP_setClockStopMode(MCBSPB_BASE, MCBSP_CLOCK_SPI_MODE_NO_DELAY);

    //
    // Set Rx & Tx delay to 1 cycle.
    //
    McBSP_setRxDataDelayBits(MCBSPB_BASE, MCBSP_DATA_DELAY_BIT_0);
    McBSP_setTxDataDelayBits(MCBSPB_BASE, MCBSP_DATA_DELAY_BIT_0);

    //
    // Set CLKX & FSX source as sample rate generator.
    //
    McBSP_setTxClockSource(MCBSPB_BASE, MCBSP_EXTERNAL_TX_CLOCK_SOURCE);
    McBSP_setRxClockSource(MCBSPB_BASE, MCBSP_INTERNAL_RX_CLOCK_SOURCE);
    McBSP_setTxFrameSyncSource(MCBSPB_BASE, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE);
    McBSP_setRxFrameSyncSource(MCBSPB_BASE, MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE);

    //
    // Set Tx and Rx clock and frame-sync polarity.
    //
    McBSP_setTxFrameSyncPolarity(MCBSPB_BASE, MCBSP_TX_FRAME_SYNC_POLARITY_LOW);
    McBSP_setTxClockPolarity(MCBSPB_BASE, MCBSP_TX_POLARITY_FALLING_EDGE);
    McBSP_setRxClockPolarity(MCBSPB_BASE, MCBSP_RX_POLARITY_RISING_EDGE);

    //
    // Initialize McBSP data length.
    //
    McBSP_setRxDataSize(MCBSPB_BASE, MCBSP_PHASE_ONE_FRAME,
                        MCBSP_BITS_PER_WORD_16, 5);
    McBSP_setTxDataSize(MCBSPB_BASE, MCBSP_PHASE_ONE_FRAME,
                        MCBSP_BITS_PER_WORD_16, 5);

    //
    // Set frame synchronization pulse period to 1 CLKG cycle.
    //
    McBSP_setFrameSyncPulsePeriod(MCBSPB_BASE, 0);

    //
    // Set frame-sync pulse width to 1 CLKG cycle.
    //
    McBSP_setFrameSyncPulseWidthDivider(MCBSPB_BASE, 0);

    //
    // Set the trigger source for internally generated frame-sync pulse.
    //
    McBSP_setTxInternalFrameSyncSource(MCBSPB_BASE,
                                       MCBSP_TX_INTERNAL_FRAME_SYNC_DATA);

    //
    // Set LSPCLK as input source for sample rate generator.
    //
    McBSP_setTxSRGClockSource(MCBSPB_BASE, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK);

    //
    // Set Divide down value for CLKG.
    //
    McBSP_setSRGDataClockDivider(MCBSPB_BASE, 0);

    McBSP_disableRxFrameSyncErrorDetection(MCBSPB_BASE);

    //
    // Set no external clock sync for CLKG.
    //
    McBSP_disableSRGSyncFSR(MCBSPB_BASE);

    //
    // Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
    // Total cycles required = 2*(SYSCLK/LSPCLK). In this example
    // LSPCLK = SYSCLK/4.
    //
    MCBSP_CYCLE_NOP(8);

    //
    // Enable Sample rate generator and wait for at least 2 CLKG clock cycles.
    //
    McBSP_enableSampleRateGenerator(MCBSPB_BASE);
    McBSP_enableFrameSyncLogic(MCBSPB_BASE);

    //
    // Wait for CPU cycles equivalent to 2 CLKG cycles-init delay.
    // Total cycles required = 2*(SYSCLK/(LSPCLK/(1+CLKGDV_VAL))). In this
    // example LSPCLK = SYSCLK/4 and CLKGDV_VAL = 1.
    //
    MCBSP_CYCLE_NOP(16);

    //
    // Release Rx, Tx and frame-sync generator from reset.
    //
    McBSP_enableTransmitter(MCBSPB_BASE);
    McBSP_enableReceiver(MCBSPB_BASE);

    //
    // Wait for CPU cycles equivalent to 2 SRG cycles-init delay.
    // Total cycles required = 2*(SYSCLK/LSPCLK). In this example
    // LSPCLK = SYSCLK/4.
    //
    MCBSP_CYCLE_NOP(8);
}

Regards

Varun

over 6 years ago

0 Mark Labbato over 6 years ago

Guru 30330 points

Varun,

Yes, the McBSP can handle larger than 32 bit data at a time. The an important thing to note is that the McBSP aslo requires a toggle on the FSX pin between each 32bit word.

Please go through the table "Bit Values Required to Configure the McBSP as an SPI Slave" verify that you are setting up these bits correctly. I have seen where if just one bit is off, the McBSP can operate in undefined ways even when appearing to work some of the time.

Link to the TRM: http://www.ti.com/lit/spruhm8

Please meticulously check your configuration.

-Mark

0 Mark Labbato over 6 years ago in reply to Mark Labbato

Guru 30330 points

Varun,

It has been more than 10 days since you last replied. I am assuming that you have resolved your issue and will close this thread. If you have additional questions, please reply here. If the thread locks (30 days after this post without activity), use the "Ask a related question" button on this page to make a new thread.

Thanks,
Mark

0 Varun Malladi over 6 years ago in reply to Mark Labbato

Intellectual 270 points

Hi Mark,
Sorry I was not able to reply to your message. I asked another question please do have a look at it. And yes, thanks for that info though. I am closing this thread!
Thanks!

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TMS320F28379D: MCBSP SPI More than 32 Bits Slave Receive