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Hello,
I'm new to both the C2000 and CCS. I've modified the "BlinkingLED" example code for the F28027 Piccolo controlSTICK to drive one HRPWM, and sample three ADC channels sequentially triggered from the same ePWM module. I'm using the Flash build configuration provided, and when I enter debug mode, the processor halts because I'm apparently getting an illegal operation (ISR_ILLEGAL()).
The RAM size of the F28027 is only 6k, so I'm wondering if I'm overrunning the RAM (stack?). Except that when I don't enable interrupts (IER, EINT, and ERTM commented out), both the HRPWM and the ADC conversions appear to be working.
Am I doing something wrong with the configuration, or am I over-running the RAM? If it's the latter, how do I use CCS to see this?
The modified code is attached, along with the Flash linker command file provided with the BlinkingLED example.
//----------------------------------------------------------------------------------
// FILE: BlinkingLED-Main.C
//
// Description: This program blinks LD2 on the Piccolo controlSTICK at a
// frequency given by the CPU timer period register. Change the
// register/bits CpuTimer0Regs.PRD.all to change the frequency of
// the LED (LD2).
//
// Target: TMS320F2802x or TMS320F2803x families (Piccolo)
//
//----------------------------------------------------------------------------------
// $TI Release:$ V1.1
// $Release Date:$ 26 Oct 2009 - BRL
//----------------------------------------------------------------------------------
//
// PLEASE READ - Useful notes about this Project
// Although this project is made up of several files, the most important ones are:
// "BlinkingLED-Main.c" - this file
// - Application Initialization, Peripheral config
// - Application management
// - Slower background code loops and Task scheduling
// "BlinkingLED-DevInit_F28xxx.c"
// - Device Initialization, e.g. Clock, PLL, WD, GPIO mapping
// - Peripheral clock enables
// The other files are generally used for support and defining the registers as C
// structs. In general these files will not need to be changed.
// "F28027_RAM_BlinkingLED.CMD" or "F28027_FLASH_BlinkingLED.CMD"
// - Allocates the program and data spaces into the device's memory map.
// "DSP2802x_Headers_nonBIOS.cmd" and "DSP2802x_GlobalVariableDefs.c"
// - Allocate the register structs into data memory. These register structs are
// defined in the peripheral header includes (DSP2802x_Adc.h, ...)
//
//----------------------------------------------------------------------------------
#include "PeripheralHeaderIncludes.h"
#include "DSP28x_Project.h"
#include "DSP2802x_EPwm_defines.h"
#ifndef DSP2802x_EPWM_DEFINES_H
#include "DSP2802x_EPwm_defines.h"
#endif
#ifndef DSP2802x_DEVICE_H
#include "PeripheralHeaderIncludes.h"
#endif
// PWM Frequency Definition
#define SYSCLK_FREQ_MHZ 60 // PWM Clock set to SYSCLKOUT = 60MHz
#define PWM_FREQ_KHZ 200
#define PWM_PERIOD_CNTS ((Uint32)SYSCLK_FREQ_MHZ*1000 / PWM_FREQ_KHZ)
// ADC Triggering via ePWM's CMPB
#define ADC_CNTS_PER_uS SYSCLK_FREQ_MHZ
#define MICSEC_TO_NS 1000 // 1000ns / 1us
#define ADC_TRIGGER_TIME_NS 200 // Trigger ADC 200ns after PWM counter resets to zero
#define ADC_TRIG_CNTS (ADC_TRIGGER_TIME_NS*ADC_CNTS_PER_uS / MICSEC_TO_NS) // Be careful of truncation error
// Register constants
#define DUTY_COARSE (EPwm2Regs.CMPAM.half.CMPA) // Set PWM Duty Cycle with coarse resolution (uses only the ePWM register)
#define DUTY_FINE (EPwm2Regs.CMPAM.all) // Set PWM Duty Cycle with fine resolution (uses ePWM register AND HRPWM 8-bit extension)
#define ADC_TRIGGER (EPwm2Regs.CMPB) // ePWM's 16-bit CMPB register being used to trigger ADC SOC
// PWM Duty Cycle Limits for normal operation
#define MAX_PWM_CNT_COARSE ((PWM_PERIOD_CNTS*90 + 50) / 100) // 90% PWM
#define MIN_PWM_CNT_COARSE ((PWM_PERIOD_CNTS*10 + 50) / 100) // 10% PWM
#define MAX_PWM_CNT_FINE (((PWM_PERIOD_CNTS<<8)*90 + 50) / 100) // 90% HRPWM
#define MIN_PWM_CNT_FINE (((PWM_PERIOD_CNTS<<8)*10 + 50) / 100) // 10% HRPWM
// PWM Macros
#define M_ForceDutyCycleZero() (DUTY_FINE = ( 0x000000 << 8 )) // Bypasses any duty cycle limits of the other macros
#define M_SetPWMDutyCoarse(x) (DUTY_COARSE = ( x & 0xFFFF ) ) // Limit to 16-bits (size of CMPA register)
#define M_SetPWMDutyFine(x) (DUTY_FINE = ( x & 0xFFFFFF) << 8 ) // Limit value sent to size of CMPA(16) + CMPAHR(8) = 24 bits, then Left Shift by 8 (LSByte is Reserved)
#define M_SetADCTrigger() (ADC_TRIGGER = ( ADC_TRIG_CNTS & 0xFFFF ) )
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// FUNCTION PROTOTYPES
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
void DeviceInit(void);
void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
void InitADC(void);
void RunDutyCycleTest(void);
interrupt void adc_isr(void);
void InitPWM(void);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// VARIABLE DECLARATIONS - GENERAL
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Used for running BackGround in flash and the ISR in RAM
extern Uint16 RamfuncsLoadStart, RamfuncsLoadEnd, RamfuncsRunStart;
Uint16 m_ADCINA1 = 0;
Uint16 m_ADCINB7 = 0;
Uint16 m_ADCINA7 = 0;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// MAIN CODE - starts here
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
void main(void)
{
static Uint16 ToggleLEDCnt = 0;
//=================================
// INITIALISATION - General
//=================================
DeviceInit(); // Device Life support & GPIO mux settings
// Only used if running from FLASH
// Note that the variable FLASH is defined by the compiler (-d FLASH)
#ifdef FLASH
// Copy time critical code and Flash setup code to RAM
// The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
// symbols are created by the linker. Refer to the linker files.
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM
InitFlash(); // Call the flash wrapper init function
#endif //(FLASH)
// reassign ADC ISR after Pie Vector Table has been initialized via DeviceInit()
EALLOW; // This is needed to write to EALLOW protected register
// PieVectTable.ADCINT1 = &adc_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// initialize PWM. Initial duty cycle is 0%.
InitPWM();
// Initialize ADC
InitADC();
// Enable INT 10.3 in the PIE
PieCtrlRegs.PIEIER10.bit.INTx3 = 1; // Set PIE Interrupt Enable bit for INT group 10, bit 3 (corresponding to ADCINT3)
// Initialize Period of CPU Timers
// Timer period definitions found in PeripheralHeaderIncludes.h
CpuTimer0Regs.PRD.all = uSec145; // 500ms * 2(# of LED states) = 1s blink rate
// CpuTimer1Regs.PRD.all = mSec1000;
// CpuTimer2Regs.PRD.all = mSec5000;
//=================================
// INTERRUPT INITIALISATION (not needed in this example)
// (best to run this section after other initialisation)
//=================================
// Enable Peripheral, global Ints and higher priority real-time debug events:
IER |= M_INT10;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//=================================
// Forever LOOP
//=================================
// Loop Forever
for(;;) //infinite loop
{
if(CpuTimer0Regs.TCR.bit.TIF == 1)
{
// clear flag
CpuTimer0Regs.TCR.bit.TIF = 1;
if( ToggleLEDCnt++ >= 3448 )
{
ToggleLEDCnt = 0;
//Toggle GPIO34 (LD2, Red)
GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1;
// HW Test - straight 90% duty cycle = 69120 counts for HRPWM
// M_SetPWMDutyFine( 69120 );
// Uncomment to bypass ADC isr.
// m_ADCINA1 = AdcResult.ADCRESULT0;
// m_ADCINA7 = AdcResult.ADCRESULT1;
// m_ADCINB7 = AdcResult.ADCRESULT2;
}
else
{
// HW Test - straight 20% duty cycle = 38400 counts for HRPWM
// M_SetPWMDutyFine( 15360 );
}
// vary duty cycle as a test
// RunDutyCycleTest();
M_SetPWMDutyFine( 38400 );
// m_ADCINA1 = AdcResult.ADCRESULT0;
// m_ADCINA7 = AdcResult.ADCRESULT1;
// m_ADCINB7 = AdcResult.ADCRESULT2;
}
}
} //END MAIN CODE
void InitADC(void)
{
Uint16 i = 0;
EALLOW;
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power up band gap
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power up reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power up rest of ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // set timing to 13cycles as required by ADC module
for(i=0; i<5000; i++){} // wait 60000 cycles = 1ms (each iteration is 12 cycles)
// Configure ADC
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; // Use internal 3.3v reference
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // create INT pulses 1 cycle prior to output latch (at end of conversion)
AdcRegs.ADCCTL2.bit.ADCNONOVERLAP = 0; // Allow overlap of conversion w/ next sample
AdcRegs.ADCCTL2.bit.CLKDIV2EN = 0; // ADC Clk = CPU Clock = 60MHz here
AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 0x03; // Force priority to be (Highest->Lowest: SOC0->SOC2)
// Use a single Trigger (ePWM2, SOCA) to cause simultaneous sample requests and let
// the SOCPRIORITY setting determine the order. ADCNONOVERLAP register bit is cleared to allow
// sampling the next signal while the previous one gets converted.
// SOC0 / EOC0 used for ADCINA1 (Vbat + Ibat*0.05)
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0x01; // set SOC0 channel select to ADCINA1
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 0x07; // set SOC0 start trigger on EPWM2, ADCSOCA
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x06; // set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1) = 166.67ns at 60MHz ADC Clk
// SOC1 / EOC1 used for ADCINA7 (Buck Vout)
AdcRegs.ADCSOC1CTL.bit.CHSEL = 0x07; // set SOC1 channel select to ADCINA7
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 0x07; // set SOC1 start trigger on EPWM2, ADCSOCA
AdcRegs.ADCSOC1CTL.bit.ACQPS = 0x06; // set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1) = 166.67ns at 60MHz ADC Clk
// SOC2 / EOC2 used for ADCINB7 (Ibat)
AdcRegs.ADCSOC2CTL.bit.CHSEL = 0x0F; // set SOC2 channel select to ADCINB7
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 0x07; // set SOC2 start trigger on EPWM2, ADCSOCA
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x06; // set SOC2 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1) = 166.67ns at 60MHz ADC Clk
// Set up interrupts (see DSP2802x_DefaultISR.h for default ISR definitions)
// Can monitor ADCINTFLG bits to make sure the conversions have occurred, but
// should only need to actually enable interrupts for the last conversion (EOC2 -> ADCINB7 in this case)
// to enter an ISR to get all data after all 3 conversions are complete.
AdcRegs.INTSEL3N4.bit.INT3E = 1; // enable ADCINT3
AdcRegs.INTSEL3N4.bit.INT3SEL = 0x02; // Trigger ADCINT3 using EOC2 (per above, corresponding to ADCINB7 -> Ibat)
AdcRegs.INTSEL3N4.bit.INT3CONT = 0; // 0: disable continuous sample mode
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1; // W1C - Clear Interrupt Flag
EDIS;
return;
}
void InitPWM(void)
{
// Time-base registers
EPwm2Regs.TBPRD = PWM_PERIOD_CNTS; // Set timer period, PWM frequency = 1 / period
EPwm2Regs.TBPHS.all = 0; // Time-Base Phase Register
EPwm2Regs.TBCTR = 0; // Time-Base Counter Register - initialize to zero
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load for period
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count-up mode: used for edge-aligned PWM
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // Disable Synchronization output signal
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Together HSPCLKDIV and CLKDIV form the PWM clock pre-scaler
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // as: TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV) = SYSCLKOUT = 60MHz, here
// Setup shadow register load on ZERO
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // CMPA register is in shadow register mode (double buffer)
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load CMPA register from its shadow on CTR=Zero (PWM Rising Edge per below)
// Set Duty Cycle (CMPA used. See pwm.h macro and constant definitions)
M_ForceDutyCycleZero(); // Set duty cycle to 0% initially (This macro bypasses any minimum duty cycle constraints)
// Set up SOCA to trigger ADC
M_SetADCTrigger(); // Set CMPB to trigger SOCA
EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable ADC SOCA pulse
EPwm2Regs.ETSEL.bit.SOCASEL = 6; // Generate SOCA pulse when time base counter = CMPB, when timer is incrementing
EPwm2Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate SOCA pulse
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM2A on Zero event (rising PWM edge)
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on Up-Count CompareA event (falling PWM edge)
// Set HiRes registers
EALLOW;
EPwm2Regs.HRCNFG.all = 0x0; // Initialize HiRes PWM Control Register
EPwm2Regs.HRCNFG.bit.EDGMODE = HR_FEP; // Enable HiRes control on Falling edge
EPwm2Regs.HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR controls the MEP
EPwm2Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO; // Shadow load on CTR=Zero
EDIS;
return;
}
void RunDutyCycleTest(void)
{
static Uint32 nTestDutyCycle = 0;
// Increment duty cycle and wrap around.
if( nTestDutyCycle++ > MAX_PWM_CNT_FINE )
{
nTestDutyCycle = MIN_PWM_CNT_FINE;
}
M_SetPWMDutyFine( nTestDutyCycle );
return;
}
interrupt void adc_isr(void)
{
m_ADCINA1 = AdcResult.ADCRESULT0;
m_ADCINA7 = AdcResult.ADCRESULT1;
m_ADCINB7 = AdcResult.ADCRESULT2;
AdcRegs.ADCINTFLGCLR.bit.ADCINT3 = 1; // W1C - Clear Interrupt Flag
// PieCtrlRegs.PIEACK.bit.ACK10 = 1; // W1C - Clear the PIE ACK bit for Group 10 to enable next PIE interrupt.
return;
}
//============================================================================
//============================================================================
//
// FILE: BlinkingLED-DevInit_F2802x.c
//
// TITLE: Device initialization for F2802x series
//
// Version: 1.0
//
// Date: 22 Oct 08 BRL
//============================================================================
//============================================================================
#include "PeripheralHeaderIncludes.h"
// Functions that will be run from RAM need to be assigned to
// a different section. This section will then be mapped to a load and
// run address using the linker cmd file.
#pragma CODE_SECTION(InitFlash, "ramfuncs");
#define Device_cal (void (*)(void))0x3D7C80
void DeviceInit(void);
void PieCntlInit(void);
void PieVectTableInit(void);
void WDogDisable(void);
void PLLset(Uint16);
void ISR_ILLEGAL(void);
//--------------------------------------------------------------------
// Configure Device for target Application Here
//--------------------------------------------------------------------
void DeviceInit(void)
{
WDogDisable(); // Disable the watchdog initially
DINT; // Global Disable all Interrupts
IER = 0x0000; // Disable CPU interrupts
IFR = 0x0000; // Clear all CPU interrupt flags
// The Device_cal function, which copies the ADC & oscillator calibration values
// from TI reserved OTP into the appropriate trim registers, occurs automatically
// in the Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC and oscillators to function according
// to specification.
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)(); // Auto-calibrate from TI OTP
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;
// Switch to Internal Oscillator 1 and turn off all other clock
// sources to minimize power consumption
EALLOW;
SysCtrlRegs.CLKCTL.bit.INTOSC1OFF = 0;
SysCtrlRegs.CLKCTL.bit.OSCCLKSRCSEL=0; // Clk Src = INTOSC1
SysCtrlRegs.CLKCTL.bit.XCLKINOFF=1; // Turn off XCLKIN
SysCtrlRegs.CLKCTL.bit.XTALOSCOFF=1; // Turn off XTALOSC
SysCtrlRegs.CLKCTL.bit.INTOSC2OFF=1; // Turn off INTOSC2
EDIS;
// SYSTEM CLOCK speed based on internal oscillator = 10 MHz
// 0xC = 60 MHz (12)
// 0xB = 55 MHz (11)
// 0xA = 50 MHz (10)
// 0x9 = 45 MHz (9)
// 0x8 = 40 MHz (8)
// 0x7 = 35 MHz (7)
// 0x6 = 30 MHz (6)
// 0x5 = 25 MHz (5)
// 0x4 = 20 MHz (4)
// 0x3 = 15 MHz (3)
// 0x2 = 10 MHz (2)
PLLset(0xC); // choose from options above
// Initialise interrupt controller and Vector Table
// to defaults for now. Application ISR mapping done later.
PieCntlInit();
PieVectTableInit();
EALLOW; // below registers are "protected", allow access.
// LOW SPEED CLOCKS prescale register settings
SysCtrlRegs.LOSPCP.all = 0x0002; // Sysclk / 4 (15 MHz)
SysCtrlRegs.XCLK.bit.XCLKOUTDIV=2;
// PERIPHERAL CLOCK ENABLES
//---------------------------------------------------
// If you are not using a peripheral you may want to switch
// the clock off to save power, i.e. set to =0
//
// Note: not all peripherals are available on all 280x derivates.
// Refer to the datasheet for your particular device.
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
//------------------------------------------------
SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 0; // COMP1
SysCtrlRegs.PCLKCR3.bit.COMP2ENCLK = 0; // COMP2
//------------------------------------------------
SysCtrlRegs.PCLKCR0.bit.I2CAENCLK = 0; // I2C
//------------------------------------------------
SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 0; // SPI-A
//------------------------------------------------
SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 0; // SCI-A
//------------------------------------------------
SysCtrlRegs.PCLKCR1.bit.ECAP1ENCLK = 0; //eCAP1
//------------------------------------------------
SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 0; // ePWM1
SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 0; // ePWM3
SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 0; // ePWM4
//------------------------------------------------
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK
//------------------------------------------------
//--------------------------------------------------------------------------------------
// GPIO (GENERAL PURPOSE I/O) CONFIG
//--------------------------------------------------------------------------------------
//-----------------------
// QUICK NOTES on USAGE:
//-----------------------
// If GpioCtrlRegs.GP?MUX?bit.GPIO?= 1, 2 or 3 (i.e. Non GPIO func), then leave
// rest of lines commented
// If GpioCtrlRegs.GP?MUX?bit.GPIO?= 0 (i.e. GPIO func), then:
// 1) uncomment GpioCtrlRegs.GP?DIR.bit.GPIO? = ? and choose pin to be IN or OUT
// 2) If IN, can leave next to lines commented
// 3) If OUT, uncomment line with ..GPACLEAR.. to force pin LOW or
// uncomment line with ..GPASET.. to force pin HIGH or
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
// GPIO-00 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0; // 0=GPIO, 1=EPWM1A, 2=Resv, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO0 = 1; // uncomment if --> Set Low initially
GpioDataRegs.GPASET.bit.GPIO0 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-01 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0; // 0=GPIO, 1=EPWM1B, 2=EMU0, 3=COMP1OUT
GpioCtrlRegs.GPADIR.bit.GPIO1 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO1 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO1 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-02 - PIN FUNCTION = PWM Output
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // 0=GPIO, 1=EPWM2A, 2=Resv, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO2 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPACLEAR.bit.GPIO2 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO2 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-03 - PIN FUNCTION = "Disable PWM" -- Connects to Gate Driver LS input
// Pulling this pin low disables the low-side driver.
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0; // 0=GPIO, 1=EPWM2B, 2=Resv, 3=COMP2OUT
GpioCtrlRegs.GPADIR.bit.GPIO3 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPACLEAR.bit.GPIO3 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO3 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-04 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0; // 0=GPIO, 1=EPWM3A, 2=Resv, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO4 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO4 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO4 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-05 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0; // 0=GPIO, 1=EPWM3B, 2=Resv, 3=ECAP1
GpioCtrlRegs.GPADIR.bit.GPIO5 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO5 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO5 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-06 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // 0=GPIO, 1=EPWM4A, 2=SYNCI, 3=SYNCO
GpioCtrlRegs.GPADIR.bit.GPIO6 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO6 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO6 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-07 - PIN FUNCTION = "Start-ON" -- Tied to Hysteretic D-F/F "/PR" line.
// Start w/ this line high (and GPIO-12 Low) to hold the F/F output in reset.
GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 0; // 0=GPIO, 1=EPWM4B, 2=SCIRX-A, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO7 = 1; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO7 = 1; // uncomment if --> Set Low initially
GpioDataRegs.GPASET.bit.GPIO7 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-08 - GPIO-11 Do Not Exist
//--------------------------------------------------------------------------------------
// GPIO-12 - PIN FUNCTION = "Enable_Bng_Bng" -- Start as Low to disable hysteretic
// current control (see also GPIO-07).
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0; // 0=GPIO, 1=TZ1, 2=SCITX-A, 3=Resv
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPACLEAR.bit.GPIO12 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO12 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-13 - GPIO-15 Do Not Exist
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
// GPIO-16 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // 0=GPIO, 1=SPISIMO-A, 2=Resv, 3=TZ2
GpioCtrlRegs.GPADIR.bit.GPIO16 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO16 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO16 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-17 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 0; // 0=GPIO, 1=SPISOMI-A, 2=Resv, 3=TZ3
GpioCtrlRegs.GPADIR.bit.GPIO17 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO17 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO17 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-18 - PIN FUNCTION = "LOAD #2" -- Output High switches on Load #2
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // 0=GPIO, 1=SPICLK-A, 2=SCITX-A, 3=XCLKOUT
GpioCtrlRegs.GPADIR.bit.GPIO18 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPACLEAR.bit.GPIO18 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO18 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-19 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // 0=GPIO, 1=SPISTE-A, 2=SCIRX-A, 3=ECAP1
GpioCtrlRegs.GPADIR.bit.GPIO19 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO19 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO19 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-20 - GPIO-27 Do Not Exist
//--------------------------------------------------------------------------------------
// GPIO-28 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 0; // 0=GPIO, 1=SCIRX-A, 2=I2C-SDA, 3=TZ2
GpioCtrlRegs.GPADIR.bit.GPIO28 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO28 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO28 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-29 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 0; // 0=GPIO, 1=SCITXD-A, 2=I2C-SCL, 3=TZ3
GpioCtrlRegs.GPADIR.bit.GPIO29 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPACLEAR.bit.GPIO29 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPASET.bit.GPIO29 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-30 - GPIO-31 Do Not Exist
//--------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------
// GPIO-32 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; // 0=GPIO, 1=I2C-SDA, 2=SYNCI, 3=ADCSOCA
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPBCLEAR.bit.GPIO32 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPBSET.bit.GPIO32 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-33 - PIN FUNCTION = --Spare--
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 0; // 0=GPIO, 1=I2C-SCL, 2=SYNCO, 3=ADCSOCB
GpioCtrlRegs.GPBDIR.bit.GPIO33 = 0; // 1=OUTput, 0=INput
// GpioDataRegs.GPBCLEAR.bit.GPIO33 = 1; // uncomment if --> Set Low initially
// GpioDataRegs.GPBSET.bit.GPIO33 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
// GPIO-34 - PIN FUNCTION = LED for F28027 USB dongle, and "LOAD #1" -- Setting high enables Load #1
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // 0=GPIO, 1=COMP2OUT, 2=EMU1, 3=Resv
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1; // 1=OUTput, 0=INput
GpioDataRegs.GPBCLEAR.bit.GPIO34 = 1; // uncomment if --> Set Low initially (Red LD2 On)
// GpioDataRegs.GPBSET.bit.GPIO34 = 1; // uncomment if --> Set High initially
//--------------------------------------------------------------------------------------
EDIS; // Disable register access
}
//============================================================================
// NOTE:
// IN MOST APPLICATIONS THE FUNCTIONS AFTER THIS POINT CAN BE LEFT UNCHANGED
// THE USER NEED NOT REALLY UNDERSTAND THE BELOW CODE TO SUCCESSFULLY RUN THIS
// APPLICATION.
//============================================================================
void WDogDisable(void)
{
EALLOW;
SysCtrlRegs.WDCR= 0x0068;
EDIS;
}
// This function initializes the PLLCR register.
//void InitPll(Uint16 val, Uint16 clkindiv)
void PLLset(Uint16 val)
{
volatile Uint16 iVol;
// Make sure the PLL is not running in limp mode
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
{
EALLOW;
// OSCCLKSRC1 failure detected. PLL running in limp mode.
// Re-enable missing clock logic.
SysCtrlRegs.PLLSTS.bit.MCLKCLR = 1;
EDIS;
// Replace this line with a call to an appropriate
// SystemShutdown(); function.
asm(" ESTOP0"); // Uncomment for debugging purposes
}
// DIVSEL MUST be 0 before PLLCR can be changed from
// 0x0000. It is set to 0 by an external reset XRSn
// This puts us in 1/4
if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
{
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
EDIS;
}
// Change the PLLCR
if (SysCtrlRegs.PLLCR.bit.DIV != val)
{
EALLOW;
// Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
SysCtrlRegs.PLLCR.bit.DIV = val;
EDIS;
// Optional: Wait for PLL to lock.
// During this time the CPU will switch to OSCCLK/2 until
// the PLL is stable. Once the PLL is stable the CPU will
// switch to the new PLL value.
//
// This time-to-lock is monitored by a PLL lock counter.
//
// Code is not required to sit and wait for the PLL to lock.
// However, if the code does anything that is timing critical,
// and requires the correct clock be locked, then it is best to
// wait until this switching has completed.
// Wait for the PLL lock bit to be set.
// The watchdog should be disabled before this loop, or fed within
// the loop via ServiceDog().
// Uncomment to disable the watchdog
WDogDisable();
while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1) {}
EALLOW;
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
EDIS;
}
//divide down SysClk by 2 to increase stability
EALLOW;
SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
EDIS;
}
// This function initializes the PIE control registers to a known state.
//
void PieCntlInit(void)
{
// Disable Interrupts at the CPU level:
DINT;
// Disable the PIE
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
}
void PieVectTableInit(void)
{
int16 i;
PINT *Dest = &PieVectTable.TINT1;
EALLOW;
for(i=0; i < 115; i++)
*Dest++ = &ISR_ILLEGAL;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
}
interrupt void ISR_ILLEGAL(void) // Illegal operation TRAP
{
// Insert ISR Code here
// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
asm(" ESTOP0");
for(;;);
}
// This function initializes the Flash Control registers
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
void InitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;
//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;
// CAUTION
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
asm(" RPT #7 || NOP");
}
// This function will copy the specified memory contents from
// one location to another.
//
// Uint16 *SourceAddr Pointer to the first word to be moved
// SourceAddr < SourceEndAddr
// Uint16* SourceEndAddr Pointer to the last word to be moved
// Uint16* DestAddr Pointer to the first destination word
//
// No checks are made for invalid memory locations or that the
// end address is > then the first start address.
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
{
while(SourceAddr < SourceEndAddr)
{
*DestAddr++ = *SourceAddr++;
}
return;
}
//===========================================================================
// End of file.
//===========================================================================
/*==================================================================================*/
/* User specific Linker command file for running from FLASH */
/*==================================================================================*/
/* FILE: F28027_FLASH_BlinkingLED.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/* from FLASH. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version: 1.1 */
/* */
/*----------------------------------------------------------------------------------*/
/* Copyright Texas Instruments � 2009 */
/*----------------------------------------------------------------------------------*/
/* Revision History: */
/*----------------------------------------------------------------------------------*/
/* Date | Description */
/*----------------------------------------------------------------------------------*/
/* 04/24/09 | Release 1.1 */
/*----------------------------------------------------------------------------------*/
/* Define the memory block start/length for the F28022
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2802x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
MEMORY
{
PAGE 0:
/* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
progRAM : origin = 0x008000, length = 0x000800
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Table in Boot */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Table in Boot */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Table in Boot */
BOOTROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
/* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAMM1 : origin = 0x000400, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
FLASHB : origin = 0x3F4000, length = 0x002000
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = progRAM,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.esysmem : > dataRAM, PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
SECTIONS
{
Net_terminals: > dataRAM,PAGE = 1
}
Thanks,
Nathan
Solved. This was a silly configuration issue. I had originally tried using the default ISR "ADCINT3_ISR", which I must not have initialized properly. When I switched to my own ISR, I bungled setting the Pie Vector address (main, line ). I'm now interrupting correctly assigning the address as:
EALLOW;
PieVectTable.ADCINT3 = &adc_isr;
EDIS;
