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F28335 EPWM Module Synchronization

Bulent Ustuntepe
Prodigy 165 points

Hello All,

I am trying to use all epwm modules (from epwm1 to epwm6) as synchronous. When I programmed the epwm modules according to the reference guide, there are 2 clock cycles difference between the master and slave module counters.

If I disable the synchoronization (EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE) there is no difference. What is wrong with this? In the following my code can be seen,

  EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
  EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Master module

  EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;   // Sync down-stream module

  EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;  
  EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;   
  EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;  

  • 0
    TI__Guru* 91235 points

    Bulent,

    The delay from internal master module to slave modules is given by (page 29 of SPRUG04):

    – if ( TBCLK = SYSCLKOUT): 2 x SYSCLKOUT
    – if ( TBCLK != SYSCLKOUT):1 TBCLK

    You can compensate in software for this if needed.

    -Lori

  • 0 in reply to Lori Heustess
    Prodigy 20 points

    I have met the synchronization problem, too. I put epwm1, epwm2 and epwm3 into the simulink with same settings. I generated code in ccs v3.3 and downloaded to F28335. The TBCLKSYN=1 but the three pwms are not synchronized and there are hundreds of clock cycles lead or lag between each other. Could you please tell me the simplest way to synchronize pwm?

  • 0 in reply to xiaotian zhang
    Prodigy 165 points

    Please check the following;

       EALLOW;
       SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
       EDIS;

          // Setup TBCLK
         EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD;           // Set timer period 801 TBCLKs
         EPwm1Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0
         EPwm1Regs.TBCTR = 0x0000;

        // Setup counter mode
        EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
        EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
        EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
        EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

       // Setup TBCLK
       EPwm2Regs.TBPRD = EPWM1_TIMER_TBPRD;           // Set timer period 801 TBCLKs
       EPwm2Regs.TBPHS.half.TBPHS = 0x0000;           // Phase is 0
       EPwm2Regs.TBCTR = 0x0000;                      // Clear counter
       
       // Setup counter mode
       EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
       EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
       EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT
       EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;    

        
       EALLOW;
       SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
       EDIS;

     

     

  • 0 in reply to Bulent Ustuntepe
    Prodigy 20 points

    Thank you very much, Bulent.

  • 0 in reply to xiaotian zhang
    Intellectual 305 points

    How to do timer synchronisation in multiple dsps (28335)?

  • 0 in reply to viju nair
    TI__Mastermind 24095 points

    You can bring out the syncout pulse on a pin from one device - refer to EPWMSYNCO in gpio mux.
    This can be fed as EPWMSYNCI input of another device to achieve synchronization.

    -Bharathi.