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F28335 ePWM time-based clock/counter synchronization

Yanni Zhong
Prodigy 10 points

Hello all,

The first question is what's the difference between time-based clock and  time-based  counter synchronization?

I need 4 ePWM modules. They share the same frequency. EPWM1 and EPWM2 are in phase, and EPWM3 and EPWM4 are in phase with each other respectively. But there is 180 oC delay between EPWM1 and EPWM3. 

Do I need to use time-base clock or time-base counter synchronization?

Here is part of my code in the initialization:

EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter ???

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up_down
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading; Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //The TBPRD shadow register is enabled
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module

EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x3; // Clock ratio to SYSCLKOUT 1/6 =25MHz
EPwm1Regs.TBCTL.bit.CLKDIV = 0x0; // default value 1 pu

EPwm2Regs.TBPHS.half.TBPHS = 0; // Set phase register to zero
EPwm2Regs.TBCTR = 0x0000; // Clear counter???

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up_down
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Enable phase loading ; Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0x3; // Clock ratio to SYSCLKOUT 1/10
EPwm2Regs.TBCTL.bit.CLKDIV = 0x0; // Slow just to observe on the scope 1pu

EPwm3Regs.TBPHS.half.TBPHS = 1250; // Phase is 180 deg, TBPRD=1250, Period=2500
EPwm3Regs.TBCTR = 0x0000; // Clear counter???

EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up_down
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // ENable phase loading
EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN; //COUNT DOWN ON SYNC (=180 DEG)
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC flow-through

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0x3; // Clock ratio to SYSCLKOUT 1/10
EPwm3Regs.TBCTL.bit.CLKDIV = 0x0; 

EPwm4Regs.TBPHS.half.TBPHS = 1250; // Phase is 180 DEG
EPwm4Regs.TBCTR = 0x0000; // Clear counter???

EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up_down
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // ENable phase loading
EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; //COUNT DOWN ON SYNC 
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // SYNC flow-through

EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x3; // Clock ratio to SYSCLKOUT 1/10
EPwm4Regs.TBCTL.bit.CLKDIV = 0x0; // Slow so we can observe on the scope 1pu

They all have the same frequency. Do I need to identify them in each of them, and set their HSPCLKDIV and CLKDIV?

Do I need to put the following lines for each of them to globally synchronize all enabled ePWM modules in the initialization?

   EALLOW;
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
   EDIS;

   EALLOW;
   SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
   EDIS;

Many thanks for your time.

Best Regards,

Yanni

  • 0
    TI__Mastermind 24095 points

    Hi Yanni,

    Time base clock is the clock on which EPWM module is operating. This can be System clock or a divided (pre-scaled) version of the system clock.
    Synchronization of time base between 2 PWM modules can be done using synchronization scheme.
    In your case you need to use time base synchronization to maintain required (180 degree) phase shift between EPWM1 and EPWM3.
    More details in EPWM user guide.


    -Bharathi.