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TMS320f2812 default ISRs; best practices?

Jon10541
Prodigy 170 points

I want to fill up the vector table with default ISRs that do sensible things in the event of a spurious interrupt. There is a vector table of 128 PIE vectors defined in the linker script like this:

 .vectors:  > PIE   PAGE 1

SPRU078E defines this in table 6.4. The first 32 vectors are for core interrupts, and I'm not sure how to acknowledge these. The IFR only has 16 bits, yet there are 32 interrupts. And the ones that say "not used-see PIE group X"; am I supposed to install vectors here at all?

As for the rest of the vectors, I have 12 separate dummy ISRs that know what PIE group they are in, and acknowledge the right PIEACK bit, so that a spurious interrupt doesn't kill all the interrupts in that PIE group because of failure to acknowledge the spurious interrupt. So that's pretty straightforward. Those first 32 vectors are a bit of a mystery, though.

  • 0
    TI__Guru* 91275 points

    Jon,

    For INT1 to INT12, where it says they are not used, these locations are truely not used.  Instead they are muxed interrupts in the associated PIE group.  For example, PIE group 1 will be fed into INT1 so there isn't a single vector that corresponds to INT1.   Instead you use the vectors in PIE group 1.  Same for INT2 through INT12.

    INT13 is external interrupt or timer 1

    INT14 is CPU timer 2

    DATALOG, RTOSLOG and EMUINT - you probably just want to catch these interrupts - they shouldn't occur.  BIOS may use RTOSLOG.

    NMI is an external interrupt

    ILLEGAL will occur if you fetch a bad opcode - ex code goes off in the weeds.  If this occurs during debug you probably want to halt or loop so you can figure out where it occurred.  If it happens in a production system you might want to shut things down.

    USER1 - USER12 are used by the INTR and TRAP instructions.  If you arn't using these then they shouldn't occur.

    Regards

    Lori

  • 0 in reply to Lori Heustess
    Prodigy 170 points

    Great advice, but the question remains: the IFR only has 16 bits. How do you acknowledge interrupts 16-31?

  • 0 in reply to Jon10541
    TI__Guru 63890 points

    Those particular interrupts are defined as Non-maskable interrupts and are described in Section 3.5 of the TMS320C28x DSP CPU and Instruction Set Reference Guide (SPRU430).

    The software interrupt instructions and /NMI are associated with this.  The C28x immediately approves this type of interrupt and branches to the corresponding interrupt service routine.