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2833x ePWM sync-in/out timing

Oba
Genius 16895 points

Hello,

A customer will use 2 F28335s, and ePWM sync-out of the one F28335 is connected to ePWM sync-in of the other F28335.
Then they want to know this PWM sync delay of this case.
Could anybody explain this timing? I couldn't find this detail timing in the datasheet.

Regards,
Satoshi Obata

  • 0
    TI__Guru* 91235 points

     Obata,

    The sync output pulse from the device will be 8 SYSCLKOUT cycles wide (Table 6-20 in SPRS439)

    The sync input must have a pulse width of at least 2 SYSCLKOUT cycles to be recognized (assuming no input qualification) (Table 6-21 in SPRS439)

    Once the sync input is recognized, the synchronization will occur on the next TBCLK - so it depends on the ratio between SYSCLKOUT and TBCLK. 

    The delay from internal master module to slave modules is given by:

    if( TBCLK = SYSCLKOUT), Internal Master To Internal Slave Delay = 2 SYSCLKs
    if( TBCLK != SYSCLKOUT), Internal Master To Internal Slave Delay = 1 TBCLK

    The master to slave timing seems to be missing from the users guide (it is in the specification).  I'll make sure it gets added to the next revision.

  • 0 in reply to Lori Heustess
    TI__Genius 16895 points

    Lori,

    Thanks, I tested again and confirmed it worked as you mentioned.

    Regards,
    Satoshi Obata