Hello all.
Forgive me, SPI seems to be a popular favourite at the moment.
I've got a customer who is configuring a McBSP - SPI interface on a 2812, and I'm trying to work out his maximum communication frequency limitations, in part by investigating clock to valid data out timings.
He's got some 1k resistors in all signal lines (a side effect of his application), so our estimate of his worst case timing path for a McBSP-SPI transaction would be :
PCB delay for McBSP clock out to SPI clock in – Delay for clock to valid data out of the SPI slave – PCB delay for SPI data out – Data setup at McBSP end.
There's a pdf attached with some workings which may express more than words. Provided this is correct, I can't work out what the clock to valid data out maximum timing value is for the SPI slave.
Based upon section 6.22 of sprs174o, I can see a minimum, but no maximum. Does anyone know what this value could be?
Kind thanks in advance, as always.
Tim
