PIE Vector Priority

Abhijit,

For all F28x processors, the golden rule of interrupts is that IF an interrupt is pending (PIEIFRx and/or peripheral register flag set, and IFR flag set) and IF that interrupt is enabled (peripheral register bit and/or PIEIERx set, IER register set, and global interrupt mask INTM bit cleared), then the interrupt will immediately be serviced (ISR executed).

IF two (or more) interrupts are pending and both are enabled, then the interrupt with highest (hardware) priority will get serviced first.  Priority in IER is INT1 is highest priority (so PIE group 1 is highest priority).  Within a PIE group, PIEx.1 is highest priority.  So for example, PIE2.4 has higher priority over PIE2.6.  PIE2.4 also has higher priority over PIE5.1.  And so on.

Now, the key thing here is that the interrupt must be enabled.  When the CPU responds to an interrupt, the INTM bit is set which disables all interrupts globally.  Therefore, in your example, you are servicing PIE9.4 when PIE9.1 gets flagged.  Unless you re-enabled the INTM bit (INTM=0), you will stay in the PIE9.4 ISR (I think also that the PIE  group bit, e.g. bit 9 here, in the IER is automatically cleared, so you would need to re-enable that as well since your example has both interrupts on the same PIE group).  If software cleared INTM bit during execution of PIE9.4, then ANY enabled interrupt will interrupt you.  Remember that priority only matters if two or more interrupts are pending at the same time and the processor needs to determine which one to service first.  Once you get into an ISR, the CPU has no knowledge that you are in an ISR.  The ISR is just like any other piece of code.  Interrupt vectoring is ONLY determined by the interrupt flags (PIEIFRx, IFR) and the enables (PIEIERx, IER, INTM bit).

Regards,

David

Hi..David,

thanks for your reply. I checked my program and I have not cleared INTM bit in side ISR routine.

I tried with your suggested way but results were not good program get stuck up some where.

My vector response is like

INTC94: ;LB INTC94

ASP

PUSH AR1H:AR0H ; 32-bit
PUSH XAR2 ; 32-bit
PUSH XAR3 ; 32-bit
PUSH XAR4 ; 32-bit
PUSH XAR5 ; 32-bit
PUSH XAR6 ; 32-bit
PUSH XAR7 ; 32-bit
PUSH XT ; 32-bit
PUSH ACC
LCR _c_int94 ;SCIB_Tx int

POP ACC
POP XT
POP XAR7
POP XAR6
POP XAR5
POP XAR4
POP XAR3
POP XAR2
POP AR1H:AR0H
NASP
IRET

 c_int94 ISR Routine looks like below,

{EALLOW;

*PIEIER9=0x0001;
NOP;NOP;NOP;NOP;NOP;NOP;NOP;NOP;

*PIEACK=0x0100;
 asm (" CLRC INTM");
asm (" OR IER, #1119h ");

EDIS;

my ISRroutine();

EALLOW;

*PIEIER9=0x000d;

EDIS;

}

with above changes, my system gets stuck up and does not work as desired . Now I am working with *PIEACK=0x0100 instruction only. With this I only get one interrupt at a time and even higher priority interrupt will not be able to interrupt lower Priority ISR as I have not cleared INTM .

Am I doing some thing wrong? Please let me know .

Any way Happy New year to You and Your Family .

Regards

Abhijit

Abhijit,

You've got me confused.  In your previous post, you show an assembly code ISR routine.  You then make a call to a C-code function from the ISR?  I'm not following what you are doing.  If you want to nest INT9.1 inside of INT9.4 (your case I believe) , you would do this:

interrupt void MyIsr9_1(void)
{
   int16 SAVE;

   IER = 0x0100;       // Enable only INT9 group (for example)
   SAVE = *PIEIER9;    // Save current PIEIER9
   *PIEIER9 = 0x0001;  // enable only INT9.1 (for example)
   *PIEACK = 0x0100;   // acknowledge INT9 group
   asm(" CLRC INTM");  // re-enable global interrupts

   // put main body on ISR here

   asm(" SETC INTM");  // disable global interrupts
   *PIEIER9 = SAVE;    // restore PIEIER9
   // IER automatically restored on ISR return
}

I just quickly put down the above and didn't test it, but I think it is correct.  Also, the code you put in your posts was using register pointers such as *PIEIER9, so I continued to use those for illustration.  Users typically use the peripheral header file structures instead of pointers.

Regards,

David

David,

do not confus.

My upper assembley part was just to give you an idea that I have made necessary context saving before jumping to ISR C_int94() and after returing from that ISR routine I have again retrived the saved registers.

I will check your modifications as suggested and let you know.  I always use register pointer as it is very simple for me to remember.

regards

Abhijit

Abhijit Kelkar said:

I always use register pointer as it is very simple for me to remember.

You will find the peripheral register structures are better on C28x.  They generate more efficient code with this architecture than register pointers do.  They also have the bitfields defined, so you don't have to generate bit masks yourself (which is prone to mistakes).  The editor auto-complete feature also makes them easy to use.  All you need to do is know the name of the peripheral.  The structures all start with NameRegs.  For example, AdcRegs, or DmaRegs.  The auto-complete will take care of the rest.  It would be worth your while to give them a try.

You can find the F281x header files here: http://www.ti.com/litv/zip/sprc097

- David