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F2802x & F2803x ADC result timing

Ian Yeh
Prodigy 190 points

i use F2802x to do some experimenst. i have two problem:

(1) according to user's guide, in sequential mode / early interupt pulse , the ADC's result can be read after 15 adc clock (can be read at 16th clocks). CPU takes 9 clocks to go into interrupt service routine, and the the actual reading occurs at 6th pipeline phase. In other words, i can get the adc result (1(ECO pulse) + 9(ISR process) + 6(pipeline) = 16) even if the reading instuction is 1st line in ISR?

(2) i usually get the wrong ADC result at the 1st time ADC. (use late interrupt pulse)

  • 0
    TI__Guru 60865 points

    (1) Yes, even in early interrupt mode I don't think you can get into the ISR and read the ADC result the exact cycle it becomes available.  If you want to do this, you can trigger the ISR from and earlier SOC (if you have one) or from the trigger source of the ADC (e.g. if the SOC is triggered by ePWM, then have PWM generate interrupt).

    (2) Are you aware of the first sample issue in the errata?  If this is something different than the errata, can you elaborate on the issue?