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F2810　TX EMPTY bit

Michi Yama
Guru 10030 points


Hi,

I would like to know the timing that TX EMPTY flag is set High.

I checked the E2E topics as the following.

・ http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/128393.aspx?pi65721=1

・ http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/178210/650209.aspx

The both topics are same issue that TX EMPTY flag is set High before STOP bit  send out from TXD pin. And both topics are not completed. So I can't find the answer.

TX EMPTY flag set timing is very important for our customer.

Because our customer checks the TX EMPTY flag. And RS485 driver is disabled when TX EMPTY flag set to high.

Now customer has a symptom that STOP bit is not appeared on RS485 bus line.  I suspect TX EMPTY flag timing is too early than STOP bit send out.

So I would like to know  the exact timing.

Please let me know.

I appreciate quick reply.

Best regards,

Michi

 

  • 0
    Guru 10030 points

    Hi,

    Probably I think it is impossible to use TX EMPTY flag for recognition of STOP bit.

    But my customer would like to recognize that the STOP bit was shifted out by some signal or flag because of  reducing software overhead.

    Is there some signal or flag for doing it?

    I appreciate quick reply.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Guru* 87155 points

    Michi,

    In FIFO mode, there is no any signal that indicates the shift out of STOP bit.  Only status bits available in FIFO mode are TXFFST bits (Transmit FIFO status bits).

    Thanks and regards,
    Vamsi