ADC trigger on Concerto F28M36x

Hey Ionut,

How many signals do you need to convert?  Can you do something like:

ePWM1 SOCA triggered at first point in period

ePWM1 SOCB triggered at second point in period

ADCTRIG1 is ePWM1SOCA

ADCTRIG2 is ePWM1SOCB

SOC0-SOC7 are triggered from ADCTRIG1

SOC0-SOC7 convert external signals 0-7

SOC8-SOC15 are triggered from ADCTRIG2

SOC8-SOC15 convert external signasl 0-7 (same channel mux selection as SOC0-SOC7).

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Also, if you are using up-down count mode, it looks like SOCxSEL in the ePWM has the option of triggering on both zero and period (see table 7-84 in the TRM).

Hi Devin,

Thank you for your fast reply. Something similar like you suggest i've tried, but i don't get the expected result. The ADC interrupt is running with the same frequency as the PWM interrupt, which should be double. Do i have to setup two interrupts for the same ADC module? I need to sample 3 signals only with double the PWM freq.

I attach the ADC and PWM settings i make, maybe you can see something i am missing here.

Best regards,

Ionut

_____ADC setup:

    EALLOW;
    // Enable non-overlap mode i.e. conversion and future sampling events don't overlap
    Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1;

    // ADCINT1 is generated after AdcResults latch
    Adc1Regs.ADCCTL1.bit.INTPULSEPOS   = 1;

    // Enabled ADCINT1
    Adc1Regs.INTSEL1N2.bit.INT1E       = 1;

    // Disable ADCINT1 Continuous mode
    Adc1Regs.INTSEL1N2.bit.INT1CONT    = 0;

    // Setup EOC0 to trigger ADCINT1
    Adc1Regs.INTSEL1N2.bit.INT1SEL     = 0;

    // Set SOC0 channel select to ADC1A0 - AC Current Phase U
    Adc1Regs.ADCSOC0CTL.bit.CHSEL      = 0;
    Adc1Regs.ADCSOC8CTL.bit.CHSEL      = 0;

    // Set SOC1 channel select to ADC1A2 - AC Current Phase V
    Adc1Regs.ADCSOC1CTL.bit.CHSEL      = 2;
    Adc1Regs.ADCSOC9CTL.bit.CHSEL      = 2;

    // Set SOC2 channel select to ADC1A4 - AC Current Phase W
    Adc1Regs.ADCSOC2CTL.bit.CHSEL      = 4;
    Adc1Regs.ADCSOC10CTL.bit.CHSEL      = 4;

    // Assigning EPWM1SOCA to ADC TRIGGER 1 of the ADC module
    AnalogSysctrlRegs.TRIG1SEL.all     = 5;
    AnalogSysctrlRegs.TRIG2SEL.all     = 6;

    // Set SOCs start trigger to ADC Trigger 1 (EPWM1 SOCA) of the ADC
    Adc1Regs.ADCSOC0CTL.bit.TRIGSEL    = 5;
    Adc1Regs.ADCSOC1CTL.bit.TRIGSEL    = 5;
    Adc1Regs.ADCSOC2CTL.bit.TRIGSEL    = 5;

    Adc1Regs.ADCSOC8CTL.bit.TRIGSEL    = 6;
    Adc1Regs.ADCSOC9CTL.bit.TRIGSEL    = 6;
    Adc1Regs.ADCSOC10CTL.bit.TRIGSEL    = 6;

    // Set SOC0-5 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1) - fastest
    Adc1Regs.ADCSOC0CTL.bit.ACQPS      = 6;
    Adc1Regs.ADCSOC1CTL.bit.ACQPS      = 6;
    Adc1Regs.ADCSOC2CTL.bit.ACQPS      = 6;
    Adc1Regs.ADCSOC8CTL.bit.ACQPS      = 6;
    Adc1Regs.ADCSOC9CTL.bit.ACQPS      = 6;
    Adc1Regs.ADCSOC10CTL.bit.ACQPS     = 6;

    EDIS;

___PWM setup:

    EALLOW;

    // Settings for ADC triggers (SOCA and SOCB)
    GpioG1CtrlRegs.GPADIR.bit.GPIO8        = 1;         // Set as output for SOCA
    GpioG1CtrlRegs.GPAMUX1.bit.GPIO8    = 3;         // Set MUX to ADCSOCAO

    GpioG1CtrlRegs.GPADIR.bit.GPIO10    = 1;         // Set as output for SOCB
    GpioG1CtrlRegs.GPAMUX1.bit.GPIO10    = 3;         // Set MUX to ADCSOCBO

    EDIS;

///////////////////////////// not relevant part deleted

    // Setup triggers for ADC interrupt in Zero (only by EPwm1)
    // Set SOCA for ADC during Zero event
    EPwm1Regs.ETSEL.bit.SOCAEN         = 1;      // Enable SOCA
    EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;   // Select SOCA on Zero event (TBCTR = 0x0000)
    EPwm1Regs.ETPS.bit.SOCAPRD         = 1;      // Generate interrupt on each period

    // Set SOCB for ADC during Max event
    EPwm1Regs.ETSEL.bit.SOCBEN            = 1;     // Enable SOCB
    EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_PRD;   // Select SOCB on MAX event (TBCTR = TBPRD)
    EPwm1Regs.ETPS.bit.SOCBPRD            = 1;     // Generate pulse on 1st event

Hi Devin,

Thank you very much for your help!

I got the job done by using two interrupts as you suggested, running the same interrupt routine.

Best regards,

Ionut