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Half Bridge Inverter

Bhuvaneshwar kanade54447
Intellectual 680 points
Other Parts Discussed in Thread: TMS320F28035

Dear All,

         I am writing code for half bridge inverter using DDS method and using TMS320F28035.

I have half cycle reference sine wave look up table.

I am able to generate sine wave output of 230Vac at 300VDC. But there is lots distortion in output waveform at Zero Crossing when load is 1.6A.

I suspect that energy in Output chock is not getting dissipated near to zero crossing and PWM become equal which are unable to discharge energy from it.

My switching frequency is 12.5KHz so number of samples are 250 per cycle.

I have done some research and come to know that to reduce THD number of pulse per cycle make an important role.

How much should be the number of samples per cycle ?

As well as there was a phenomenon known as symmetric PWM and Asymmetric PWM.

How to implement asymmetric PWM ? is it reducing THD ?

Please find attached for  ouput waveform captured at 1.6A load

and 35A load

2117.Half Bridge Inverter Problem.pdf

  • 0
    Intellectual 870 points

    Hi,

    Half bridge has power limitations. Let me explain this in simple words however u can always refer to a Power Electronics Text Book to find the mathematical relations and relevant stuff. It depends on the core but no matter how good the core is, half bridge uses only one side of the BH curve. In simple words the core is energized in one direction only. This causes the ferrite core to saturate on high currents, this in turn reduces energy transfer (mutual inductance) and the energy gets trapped in the saturated inductor. Thus inductor kick backs are larger and u will have to put in bigger snubbers. Also since the BH curve and mutual inductance become non linear when pushed to limits by higher currents, the transfer function becomes non linear and thus the waveform on the output is not linear. The pwm thus induces multiple harmonics. I will not go in to further analysis, u can analyze it in pspice or just for ur understanding it is the type of distortion caused by a diode just before turning one, however the distortion is load depended and is induced on a cycle by cycle basis. As the load current increases near peaks of the sinewave so would be the distortion. U should opt for full bridge if the load is high or use a core with much higher permeability. Full bridge is the right choice

    Regards symmetric / asymmetric pwm, if I am correct the text refers to it as 2 level and 3 level pwm. In 2 level the pwm output has two levels, +ve and gnd or +ve and -ve . A triangle carrier compared with a sinewave as modulating signal in an analog comparator will produce this type of a wave form. In case of a bridge during each pulse, for mark the current flows in one direction and during space the current flows in the opposite direction. In your case for single bridge during mark the current will flow and during space the current will not flow. U always introduce dead times to make sure turnoff delay does not cause micro seconds short ckts.

    In 3 level pwm for a bridge during the +ve sine cycle for all pulses one pair of bridge fets/bjts are turned on during mark and off during space. The other pair is always off, during the -ve half cycle the other pair is turned on and off with first pair permanently off.

    Both methods have pros and cons. The 2 level being the ideal pwm type has lower distortion, 3 level is a modification of 1st and ensures much lower switching losses, avoids useless narrow pulses. Modification of the two also exist, e.g. over modulation types etc. that reduce specific harmonics.

    In your case the immense distortion is due to single bridge and ferrite core saturation and not due to pwm method, 12.5 khz is high enough to give good overall shape.

  • 0 in reply to Jawwad Hafeez
    Intellectual 680 points

    Thank For Your Reply,

              But is it possible to generate 3 level PWM ans Over Modulation PWM in TMS320F28035 and how 3 level PWM is done ?

    In current software i am using PWM counter in UP DOWN mode .

    During positive half cycle Upper IGBT is ON and lower is just compliment of the same, so for Positive half cycle upper IGBT conducts more and Lower is just compliment of that. During Negative Half Cycle  Lower IGBT turns on More and Upper is Just compliment of the Lower IGBT. Is it 2 level PWM technique how to do 3 level PWM ?

    Can you explain logic it will be more helpful ? and in previous waveform Current waveform is of output LC filter wave form and not actual output waveform.

    Once again thanks in advance.

  • 0 in reply to Bhuvaneshwar kanade54447
    Intellectual 870 points

    Hi,

    Sorry for late reply, had flu and fever for the last couple of days. Any way, I did not understand what do u mean by "lower is just compliment of the same". If that means that for each pwm pluse during mark the one bjt is on and during space the other bjt is on, then u are doing 2 level pwm. Make sure u put dead time between turning on the compliment bjt, so your seq would be,

    bjt 1 on, bjt 2 off --------- Mark

    bjt 1 off, bjt 2 off --------- Dead time

    bjt 1 off, bjt 2 on --------- Space

    bjt 1 off, bjt 2 off --------- Dead time

    For 3 level pwm normally a lookup table is used that has pwm values (pulse widths) for half sine cycle. For half cycle only on bjt e.g. the upper one is turned on and then off.  So the seq will be e.g. [bjt 1 on, bjt 2 off], [bjt 1 off, bjt 2 off] and so on.

    Again the same sequence is repeated with 2nd bjt

    [bjt 1 off, bjt 2 on], [bjt 1 off, bjt 2 off] and so on.

    U see the core is energized in one direction again and again for each pwm pulse for complete upper part of sine wave cycle. Then during 2nd half it is energized by turning on and off the 2nd bjt and holding 1st bjt off through out

  • 0 in reply to Jawwad Hafeez
    Intellectual 680 points

    Hi,

     Is there any document with images to show this process and procedure.

    Thank You

  • 0 in reply to Bhuvaneshwar kanade54447
    Intellectual 870 points

    Hi,

    Check this,

    http://www.powere.dynamictopway.com/i6.htm

    and

    www.faculty.umassd.edu/xtras/catls/resources/binarydoc/1291.ppt‎

    Plz let me know if u have a specific question.


  • 0 in reply to Jawwad Hafeez
    Intellectual 680 points

    I am writing code for half bridge inverter using DDS method and using TMS320F28035.

    I have half cycle reference sine wave look up table.

    I am able to generate sine wave output of 230Vac at 300VDC. But there is lots distortion in output waveform at Zero Crossing when load is 1.6A.

    I suspect that energy in Output chock is not getting dissipated near to zero crossing and PWM become equal which are unable to discharge energy from it.

    My switching frequency is 12.5KHz so number of samples are 250 per cycle.

    I have done some research and come to know that to reduce THD number of pulse per cycle make an important role.

    How much should be the number of samples per cycle ?

    As well as there was a phenomenon known as symmetric PWM and Asymmetric PWM.

    How to implement asymmetric PWM ? is it reducing THD ?

    Please find attached for  ouput waveform captured at 1.6A load

    and 35A load.

    I am measuring current at output, is it correct position for measuring current for controlling?

    Thank you

    5314.2117.Half Bridge Inverter Problem.pdf