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interrupts

Lukas Sk
Intellectual 305 points


Hi,

I have read chapter Peripheral interrupt expansion in TMS320x2833x, 2823x System Control and Interrupts Reference Guide and some things are unclear to me.
1) Are interrupts pulse or level based? (Does register PIEIFRx holds level form peripherals or is it set to 1 only on edge) Where is it defined?

2) Assuming pulse interrupts. Do peripheral blocks (like I2C module) generate pulse after every new interrupt request occurs or do they generate pulse only after first interrupt request occurs?

3) What is the reason that I have to clear bit in PIEACKx register in ISR handler? I can not think of any situation in what I would not do it and let interrupts from PIE group blocked.

  • 0 in reply to Igor Gorbachev
    Intellectual 305 points

    It was not useful. My question was related to sequence:

    iterrupt flag A is set in peripheral -> ... -> user ISR is run and it checks that flag A is set -> meanwhile interrupt flag B is set in peripheral -> user ISR clears A but not B and ends. Will user ISR be executed again?

    It all comes to what precisely is "An interrupt-generating event"

  • 0 in reply to Lukas Sk
    TI__Guru 61235 points

    Lukas,

    Once an interrupt flag is set, that interrupt will stay pending until it is either serviced or manually cleared.  The interrupt logic takes care of all this.  In your example, peripheral interrupt flag B is still set at the end of the A-ISR.  So, interrupt B will get serviced (evneutally, whenever it becomes the highest priority pending interrupt).  Perhaps what is confusing is if A and B are both on the same PIE interrupt.  In that case, the core IFR flag is automatically cleared when A is serviced, along with the PIEIFR flag for A.  However, as soon as the PIE is acknowledged by software in the A-ISR, the PIE will send the B interrupt through and it will flag the IFR again.

    Hope this helps.

    - David

  • 0 in reply to David M. Alter
    Intellectual 305 points

    Just to be sure. For instance:
     SCDINT is asserted -> PIEIFR is set -> ... -> PIEIFR is cleared -> user ISR is started -> NACKINT is asserted and PIEIFR is set again -> user ISR clears SCDINT and PIEACK and ends -> PIEIFR is cleared -> user ISR is started again.

    Arbiter sends "pulse" for every new asserted interrupt condittion. Is my understanding correct?

  • 0 in reply to Lukas Sk
    TI__Guru 61235 points

    Lukas,

    Yeah, the interrupts in the I2C module can be confusing.  When you get into the ISR, software reads the I2CISRC register.  This register contains a value that indicates which of the I2C interrupts you are servicing.  Reading this register also clears the corresponding flag in the I2CSTR register.  If there are remaining interrupts flagged in the I2CSTR, the I2C arbiter will load the indicator value for the highest priority remaining interrupt into the I2CISRC register, and send another interrupt request to the PIE.  When software acks the PIE in the first ISR, the PIE will then send another interrupt request to the CPU by setting the flag in the IFR again (it was already cleared automatically upon entry to the first ISR).

    Regards,

    David