I2C clock stretching detection on TMS320F2802

Francesco,

I don't believe you can do this easily.  There is nothing in the F2802 I2C registers that indicate an external slave device clock stretching.  All I can think of is that you know how long it should take for the transaction to complete with no clock stretching in place.  You could run a timer for that amount of time.  At the end of the time period, if the I2C transaction has not completed, you'd have to assume the slave is clock stretching.  Alternately, you might be able to monitor the clock line for activity using, for example, a capture unit.  Lack of activity would indicate clock stretching.  All of these approaches are rather complicated and cumbersome.  Not really sure why you need to know if the slave is clock stretching.

Regards,

David

David,

thank you for your prompt response, your conclusions are sound.  Anyhow, we have a master pooling the slave with the following sequence to detect if it is present or not:

START, SLAVE ADDRESS, R/W.......wait for slave ACK, if a timeout expires, it means that no slave are ready on the line and the application state machine of the master is reset, this leads to a new addressing phase.

After a certain number of attempts...

START, SLAVE ADDRESS, R/W.......wait for slave ACK
START, SLAVE ADDRESS, R/W.......wait for slave ACK
...
...

the slave sends the ACK:

START, SLAVE ADDRESS, R/W, ACK......

but it has no data ready and it enters in clock stretching. The problem is that master timeout expires while waiting for the slave response, the master assumes the connection is lost,
the state machine is reset and the application prepares a new addressing phase. But the slave has been already addressed and two device can't communicate anymore, because the slave
is not able to manage a new addressing phase if it has been already addressed and it has a pending DATA frame to send after the ACK.
                                   
In my opinion the problem is related with the slave behaviour, if the timeout expires on master side while slave is in clock-stretching, the slave must be able to manage the new addressing phase.
In other words the slave response must be sent meeting master timeout boundary, if (on slave side) this target is not meet, the slave must assume the master will start a new addressing sequence, hence
it must be able to discard pending DATA frame and prepare itself for a new addressing phase coming from master.

Do you share this thought?

Regards

Francesco,

Francesco Esposito said:

START, SLAVE ADDRESS, R/W.......wait for slave ACK, if a timeout expires, it means that no slave are ready on the line and the application state machine of the master is reset, this leads to a new addressing phase.

If no slave is on the bus, don't you get a NACK instead of an ACK?  The F2802 could enable the NACK interrupt (NACKINT).  In other words, you must either get an ACK or a NACK.  So I don't see why you need a timer running at this stage of the game.

Can you get rid of the timeout?  That would seem to solve the problem you are having.

- David

Dear David,

thank you for your response,

you are simply claiming that after the addressing phase of the master:

START, ADDRESS, R...

If there are no slaves on the network (SDA pulled up) the I2CSTR.NACK bit is set to 1 regardless the fact that the corresponding ISR has been enabled or not, because we are working in polling mode.

Regards

Correct.  So you should check (poll) the ACK and the NACK bits at the same time.  One of these will have to be set.  Then you don't need the timeout timer.

- David

Dear David,

timeout removed and NACK catched, hence problem solved....many thanks for your clues.

Francesco