F28377D ADC results problem

Hi Kris,

I hope you're using the sample code provided in controlSuite, right? If yes, then I've checked the sample codes myself and they work like charm. The above issue you're experiencing should not occur.

Share your setup details.

Regards,

Gautam

I have written my owm code that has some additional functionality than just adc measurements, however its these measurements that are the current problem for me now. I have used the sample code to learn but i have also imported the code to ccsv6 and run it on the F28377D but still with same results. I attached the most important part of my code regarding the adc, i dont think other parts of my code could cause trouble since no AdcaRegs are changed or similar. I can still attach more code if its really needed but it is not so easy for others to understand i have to make it understandable before i attach it here if you wonder why i didn't share all of my code. I really appreciate your help. 

/Kristoffer

EALLOW;
CpuSysRegs.PCLKCR13.bit.ADC_A = 1; //ADC module A is enabled

AdcaRegs.ADCCTL2.bit.SIGNALMODE = 0; //single-ended conversion 1=differential

AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; //12 bits resolution

AdcaRegs.ADCCTL2.bit.PRESCALE = 0; //ADCCLK = imput clock / 1.0

AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; //analog circuitry is powered up

AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //SOC0 to be triggered on EPWM1SOCA

AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // SOC0 converts channel 0, if differential is selected as conv.type 01 ADCIN0 (non-inverting) and ADCIN1 (inverting)

AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 7; //SOC1 to be triggered on EPWM2SOCA

AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; // SOC0 converts channel 0, if differential is selected as conv.type 01 ADCIN0 (non-inverting) and ADCIN1 (inverting)

AdcaRegs.ADCSOC0CTL.bit.ACQPS = 30; //(30 clkcycs)Sets the number of clock cycles to the acquisition window between 1-512

AdcaRegs.ADCSOC1CTL.bit.ACQPS = 30; //(30 clkcycs)Sets the number of clock cycles to the acquisition window between 1-512

AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0; //TRIGSEL field determines SOC0 trigger

AdcaRegs.ADCINTSOCSEL1.bit.SOC1 = 0; //TRIGSEL field determines SOC0 trigger

AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 2; //SOC0-SOC1 high priority othere SOCs are in the round robin scheme

EDIS;

 

Kristoffer,

Would you be able to try the unmodified ControlSUITE example on your ControlCARD to see if the ADC behaves as expected?  This will help us identify any potential hardware problems with the device or PCB.

-Tommy

Spot on Devin, i lowered the ADC clock to below 50 MHz and now it works as intended with my own code. Thanks to all guys who gave me help in this thread i really appreciate it.

/Kristoffer

Dear All,

I have noticed a problem with 28377D, I have 5 of them and this problem is with all of them:

I have migrated from 28335 and my analog circuit is not changed. So I have about 5k of input impedance to ADCs. Now, on any ADC, 5k is considered a good value considering the parallel capacitors. But not with 28377d!!!

Datasheet claims the input cap of the ADC is 4pF, but even with 4nF paralleled cap from outside, I can see a visible voltage drop at the moment of sampling. It means the sampling capacitor is huge.

The same results is with all of them and the funny part is that the voltage (after the drop) that I read in the oscilloscope is exactly what I get with ADCs.  So ADCs are working perfect but the sampler capacitance is a killer when you have a normal 5k impedance on your analog lines.

I have added a 4.7nF capacitor on the daughter board which is helping a bit, but not enough. And I cannot add anymore because I don't want to reduce the passband of my signals.

ADC clk:40Mhz, Sysclk 200Mhz, ADC Acq windows 200ns (39).

Please check this because this is the first time in my 10+ years of using embedded controllers, I am observing such behavior.

My ESTIMATED input capacitance of samplers is 37pF not the claimed 4pF!

Hi Pourya,

Is it possible this is related to this erratum?

Note that this will be fixed on Rev. B silicon.

Yes, yes.

Thank you. I tried to look that up but it never opened on my computer.

That makes sense. And the capacitance I estimated is the total charge being transferred by that action.

I checked it at 2.5V on the pin so: Q=2.5/(30+ESR)*5ns=0.3nC   (considering only 10ohm ESR for my 4.7nF cap which is low)

I was measuring about 0.025V drop: dQ=0.025*4.7nF=0.12nC  (and none of these numbers are really accurate so I guess 0.1 to 0.3(worst case) totally makes sense.)

Wow, I have 8 of these boards. lol $1000 wasted. I wish TI would replace them. lol

I try to reduce my impedance and create fake channels (with the same voltage so that the second sample is more accurate) to cope with this.

Thank you for looking it up.

Pourya,

Yeah, we can probably replace these kits when kits with Rev. B become available. send me an email at dcottier at ti dot com and we can work out the logistics. 

Dear All,

These are some solutions to this problem:

1. If you are designing a new board, just use opamps, arrange your signals in a way that you either use 1 channel on each adc or you use even or odds. Put signals with same nominal voltage (like 1.5V) near each other so when you switch lets say from 1.3V to 1.5V on channels for example B1 to B3, then you have the minimal effect.

2. Now either if you are designing a new board or have a board like me, THIS WILL WORK:

Remove all of the unnecessary samples (like temperature monitor,..). Then based on your input impedance (mine is about 5k), select a minimal parallel adc capacitor (do not go high, go low). I selected 10pF and soldered them on the daughter board.

Now you will get a low RC (tau). So now, you can just wait the 4Tau out!. For example, I need my samples every 25us. And I need to jump between odd and even channels on ADCb. So I just open the sampler, it shorts to gnd for 5ns, then it comes back up. After 4~5tau you will get your original signal. For my case, I actually have time to keep the windows 500ns open. So now my results are good.

Example, after switching from odd and even channels with a 500ns window and 3V in to adc, I should read 4095, and I am reading 4094 which is perfect (you can't guarantee that my 3V is actually 3V). This is the worst case scenario. So it works with a small (tiny) capacitors on the input and big windows.

But it won't work as fine If you need higher SMPS rates.

Me and my colleague are working on a Master Thesis dealing with SMPS and digital active filters that is supposed to be controlled by TI F28377Dzwt micro controller. We are having some serious problems with this circuit, we have the F2837x controlCARD R1.0. We constantly run into problems, the latest beeing that the ADC conversion really messes up a signal to be measured. We asked for help in the forums but so far no solution. We drive the ADC with an opamp so the TI employees trying to help do not seem to know the solution.

Today we found this in the forums..

 

 Which pretty much explains the problem we are seeing with our signals.

We are running out of time that we can spend on this master thesis and we would appreciate if no more problems occur that do not relate directly to the things we are trying to solve with our master thesis. I mean it is wasting a lot of time to just find solutions to issues that relates to the micro controller we are using. So the question is if it is possible to get a better working specimen of the F28377D from TI? 

 

Hi,

I am working with the F28377D and just discovered the liabilities of its ADC module.. I'm witnessing the same behaviour you described Pourya: a major voltage drop translating in ADC codes completely off. I am developing a daughter board to interface with the F28377D TI development board. My intention is to feed the output of an opamp through a simple RC antialiasing filter with a cutoff around 1MHz. I'm wiring almost all ADC inputs to an opamp output to leverage the F28377D multiplexer.

Have you experimented a little more with the ADCs and are you still suggesting to simply rely on the external capacitor to cope with the oversized internal SH capacitor ?

I'd appreciate your feedback.. Thanks a lot.

François.

Francois,

As a data point, could you provide us with the silicon revision of the F28377D on your controlCARD?

The second line of text on the chip should start with "YF*-"

if * = blank then Rev0, if * = A then RevA, if * = B then RevB

Thank you,
Brett

Hi Brett,

It is YFA-43AHZ3W

Thanks for your quick reply.

Regards,

Francois.

Hi Francois,

Typically, when selecting R and C for a LP anti-aliasing filter on the ADC input, it is helpful for S+H capacitor settling time to select C larger and R smaller for a given cutoff frequency.  This is because the external capacitor is partially pre-charged to the desired voltage at the beginning of the S+H window (this is assuming an ideal signal source; you may not always actually want to select C as large as possible, for example due to op-amp stability when driving a large capacitive load through a low resistance).  

The issue with Rev. 0 and Rev. A devices is not that the internal S+H capacitor is too large.  Instead, the issue is that the timing of the ADC input MUX is not correct on these silicon versions, resulting in multiple channels being selected by the MUX simultaneously for a short duration of time.  This results in a transient shorting of two ADC pins, which depletes the external capacitor, causing it to work against you instead of helping you.

As Dr. Shamsi has pointed out, the best you can do on these revisions is to actually select C small and R large for a given cutoff frequency, and then increase the S+H window duration (ACQPS field in the SOC configuration register) to allow adequate settling time without relying on the external capacitance to help you out. I would recommend that you do this for prototyping with the Rev. A devices that you have.  

This issue is fixed on Rev. B devices. When you get Rev. B devices, you can either leave the anti-aliasing filter as-is if you are happy with the performance (performance will only get better on Rev. B), or you can change the R and C to select C larger and R smaller and then reduce the S+H window duration to get lower latency samples and/or a higher sample rate.  

Hi Devin,

I have found this problem is still present on the Rev B silicon.

I am using the 28377D control card and docking board. I produced a stable 1.65V reference and connected it to ADCINA0-A5 using separate 1k resistors. ADIN14 and ADCIN15 are ground.

If I sample A0, A1, A2, A3, A4, A15 then I can see a 160mV glitch on the A0 pin with a time constant of around 180ns. The A1 pin has a 130mV glitch around 260ns later. There are similar glitches on the other pins.

Do you know when a silicon revision will be released that actually fixes this problem?

Andrew

Hi Andrew,

We are planning to issue another errata for Rev. B silicon, which should be fixed on Rev. C silicon.  I have attached the draft version of these errata below:

Based on the ADC input model + these errata, we can simulate what is expected for both S+H capacitor settling and ADC pin glitches for the different transitions.

Let's simulate A2 to A3 transition (this one is the easiest).  Putting everything into TINA-TI, we get a circuit that looks like this:

A few comments on the model + parameters:

Ch is the S+H capacitor.  We want to charge this to within 1/4LSB of the final value during the S+H time to ensure that none of the voltage of the previous conversion remains. We set the initial value of this as 0V and the driving voltage as 2.5V to emualte worst case change in the S+H capacitor.

Ron is the ADC switch resistance.  This is 2k on Rev. B based on the first erratum, but predicted to be much less on Rev. C.  

Cbank is the extra resistance that needs to be discharged on Rev. B devices when switching between odd and even channels.

Sample is the S+H timing switch.  It closes at t = 100ns and opens at t = 640ns to emulate a S+H window of 540ns. 

Vpin is the voltage seen on the external pin. 

Cp is the parasitic capacitance on the analog pin.  For A3, the value is 6.3pF from table 6-22 "Per-Channel Parasitic Capacitance" in the DS.

Cpin is the capacitance on the pin, external to the device.  I used 8pF to emulate a scope probe, but this may have to be adjusted based on your actual input HW (this would also include board parasitics and caps placed intentionally as the C in an R-C LP filter).

Rs is the source impedance.  You reported this as 1k.

Vs is the input voltage source.  This is set to 2.5V while Ch initial condition is 0V to emulate worst case voltage change on Ch.

The circuit on the top subtracts the voltage between Vs and Ch to determine the settling error at any point in time.  After the Sample switch is opened (t = 640ns), this value will remain the constant.

Running a transient analysis on this circuit yields the following:

The green curve is Verror and the red curve is Vpin.  With 540ns, we have settling = 158uV, which is close enough to the target of 1/4LSBs = (2.5V/4096)*(1/4) = 152uV.  The glitch expected on the pin is 2.5V - 1.4V = 1.1V.  Note that this glitch will decrease as Cpin is increased.  If I increase Cpin to 270pF, I get about a 170mV glitch (See below).  Note that in this case, ADC settling will be quite bad because the external network (not even considering the ADC input mode) has a time constant of 1kohm * 270pF = 270ns (1/4LSB settline needs 9.7 time constants).   

We can compare this to the expected performance on Rev. C.  Cbank will be deleted and Ron becomes 425 ohms.

With only a scope probe adding capacitance to the input, the circuit settles well with a S+H = 300ns.  The expected glitch on the pin is reduced to 890mV.

  With 270pF external pin capacitance, the expected glitch size becomes 110mV on Rev. C.

I think the above should give you a good idea of what to expect on Rev. B and C.  We could also simulate the A15->A0 transition, but this is a little trickier due to the parasitic DAC resistance on this pin.   I've attached all of the TINA-TI files if you want to play around with the models.

F2837xD_12B_ChSwitching_A3_RevB.TSC

F2837xD_12B_ChSwitching_A3_RevC.TSC

F2837xD_12B_ChSwitching_A0_RevB.TSC

 

Hi Devin,

Thanks for your explanations. Unfortunately the workaround solutions you provide are not really satisfactory for my application as I need fast sampling. I am working on a research publication and this issue limits the performances of my system. Any idea when revision C. will be available. Any limited beta- series you could provide me for testing? Please contact me personally if this is something we could envisage.

Regards,
François.