SCIA and SCIB Port

Minhtuan Vo,

I did not look through your code, but looking at the problem description I see that you are trying to use both SCIA and SCIB with interrupts and FIFO enhancements.  There is a headerfile example "scia_loopback_interrupts" in the latest headerfiles of F2833x devices showing the same scenario.  Please look in to the code of this example and try fixing your code.

Thanks and regards,

Vamsi

 

Vamsi,

Thanks for your help.  I am actually using that example, and everything should be the same.  Except my code does not do loopback and does not send/receive continuously.  Both TX and RX interrupt of SCIA port worked very well.  The interrupt of the SCIB RX does not seem to do anything.  SCIB interrput worked if I disable the interrupt of SCIA RX/TX as below

PieCtrlRegs.PIEIER9.bit.INTx1=0;      // PIE Group 9, INT
PieCtrlRegs.PIEIER9.bit.INTx2=0;      // PIE Group 9, INT

However, SCIA won't work after that.

Would you please take a closer look at the initial state that would allow both SCIA and SCIB working together?  Thanks.

 

Minhtuan Vo,

SCI configuration looks OK except for this note:  One good practice is to do all the configuration when SCI is in reset -> Enable TXENA, RXENA and Disable loopback when SCI is in reset.  This makes sure that SCI is ready for required configuration when it is out of reset.  If not, when it comes out of reset, it starts working as it is configured already and again it sees some changes in configuration and your code may not cover all the possible events that happen because of this change.

Apart from the above modification, you configured SCI-A and SCI-B FIFO interrupt level bits to 8 both for transmitter and receiver.  Initially when the SCI is out of reset, you will get a transmit FIFO interrupt as the transmit FIFO level is 0.  But you are not transmitting any thing in the TX ISR except clearing the interrupt flag.  Even though you clear the interrupt flag, another transmit FIFO interrupt occurs as the transmit buffer level is still 0 which is less than the TX FIFO level of 8 for which TX interrupt has been configured for.  So, SCI continuously generates TX interrupt and no data is sent in your ISR.  SCI will never receive any data because you are not transmitting any thing.  In order to receive a receive FIFO interrupt, SCI needs to receive 8 data bytes as you set RX FIFO level to 8.  But SCI is not receiving any data and hence it will never trigger a receive interrupt.  Problem is not because of using 2 SCIs. 

So, things you want to try are:

1)  Decide whether you need a transmit interrupt on not to transmit data.  If you don't want to send data through TX ISR, disable TX interrupt.  Initially send 8 bytes of data and expect a receive interrupt and in the receive interrupt, you can either ignore the data or use the data as you want.  You can transmit 8 bytes of data again in your receive ISR if you want another receive interrupt to occur.

2) Change your FIFO level match bits to the desired level:  If you want to get a receive interrupt for every byte, you need to set the RX FIFO level bits accordingly.

Hope this helps.

Let me know if you need more explanation.

Thanks and regards,
Vamsi

 

Vamsi,

Thanks for helping me to figure out the TX/RX ISR issue.  I got the RX ISR to work, but I still have a little trouble to understand the TX ISR. 

According to the SCI reference guide, Transmit FIFO will generate interrupt when the FIFO status bits (TXFFST4–0) and FIFO level bits (TXFFIL4–0 ) match (less than or equal to).

I want to initiate the TX ISR when I have enough 8 bytes of data to fill in the SCITXBUF.  Therefore, I initialize the TXFFIL4-0 with a level of 8.  Whenever the RX ISR initiates (received 8 bytes), I will extract one byte and fill the TX FIFO.  This process will continue until the TX FIFO has 8 bytes filled, so the TX ISR will be interrupted and 8 bytes will be transmited until the FIFO is empty.

That's what I wanted it to do, but it does not work that way on SCIB.

I can work around that by creating my own buffer and TX whenever it got fill, but I want to use the FIFO for better efficiency.  Would you give me a recommendation on this process?  Thank you very much.

 

Vamsi,

Thanks for clearing up my mind.  It works now.

Best regards,

Minhtuan

Hi Vamsi,

I am also using the loopback interrupt example as the basis for my program. What I didn't understand was how the TX interrupt gets triggered the first time? According to your post, that first interrupt occurred as a result of SCI coming out of reset. But how do I trigger the interrupt when I have data ready to transmit and resetting the SCI is not an option?

Thanks.

Siraj.

Siraj,

As you said you are using loopback interrupt example, I assume you are asking this question in FIFO enabled mode.  When using FIFO, if you enable TX interrupt, an interrupt will be generated as soon as you configure the SCI and release it from reset as the TX FIFO is empty. 

If you want to trigger transmit interrupt only when the data is ready, you can enable transmit interrupt when the data is ready and disable the transmit interrupt after the data transmit is done in the ISR.

Thanks and regards,

Vamsi

 

                                        

 

Thanks, Vamsi.

Using the interrupt enable makes sense. I presume the ISR would disable the interrupt after sending all bytes from a buffer.

Do you know if enabling interrupts while they are already enabled affect the sending of bytes? What would happen while the ISR is sending bytes from a ring buffer and the main loop adds more bytes to the ring buffer and then enables the SCI interrupt?

Thanks.

Siraj.

Hi all,
i've tried to make what suggested above, but i can't reach anything else than a black screen in terminal. I've setted SCIBAUD to operate on 9600 (my COM port work at this baud), but i can't do anything. If i put something in terminal, no interrupt is called.
The only available solution is to create a polling function, with a timer that at each defined timeout check if buffer RX buffer contains something?

Thanks a lot.
Luca