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SCIA and SCIB Port

Minhtuan Vo
Intellectual 300 points


I'm trying to run the example scia_loopback_interrupts as an guide line for my application on SCIA and SCIB.  I created two sifferent applications, and each of them is for SCIA and SCIB, respectively.  Both applications worked perfectly well.  However, when I have them joint together, only SCIA worked, and SCIB did not work at all.  I understood that SCIA has higher priority than SCIB, but when SCIA (TX/RX) does not interrupt, SCIB interrupt should run when the SCIB port receive a character.  Is there any other setting in the initilization that I missed? 

Here is my code

//////////////////////////////////////  SCIA Port  /////////////////////////////////////////////////

interrupt void sciaTxFifoIsr(void)
{

    SciaRegs.SCIFFTX.bit.TXFFINTCLR=1;  // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;        // Issue PIE ACK
}

interrupt void sciaRxFifoIsr(void)
{
   
    SciaRegs.SCITXBUF = 0x41;   // send an "A"
    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;     // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;     // Clear Interrupt flag

    PieCtrlRegs.PIEACK.all|=0x100;         // Issue PIE ack
}

void scia_fifo_init()
{
    SciaRegs.SCICCR.bit.SCICHAR = 7;  //  1 stop bit,  No loopback
                                     //  No parity,8 char bits,
    SciaRegs.SCICCR.bit.LOOPBKENA = 1;   //  Disable loop back test mode
                                     //  async mode, idle-line protocol
    SciaRegs.SCICTL1.all =0x0000;     // disenable TX, RX, internal SCICLK,
                                     //  Disable RX ERR, SLEEP, TXWAKE
       // Issue software reset
    SciaRegs.SCICTL2.bit.TXINTENA =1;  // Enable TXRDY interrupt
    SciaRegs.SCICTL2.bit.RXBKINTENA =1;  // Enable RXRYD/BRKDT interrupt
    SciaRegs.SCIHBAUD = 0x0001;
    SciaRegs.SCILBAUD = 0x0044;

    SciaRegs.SCIFFTX.bit.SCIRST = 1;  // Resume SCI FIFO TX/RX
    SciaRegs.SCIFFTX.bit.SCIFFENA = 1;  // Enable SCI FIFO enhancement
    SciaRegs.SCIFFTX.bit.TXFFIENA = 1;  // TX FIFO interrupt based on TXFFIVL match
    SciaRegs.SCIFFTX.bit.TXFFIL = 8;  // TX FIFO interrupt level bits

    SciaRegs.SCIFFRX.bit.RXFFIENA = 1;  // RX FIFO interrupt based on RXFFIVL match
    SciaRegs.SCIFFRX.bit.RXFFIL = 8;  // RX FIFO interrupt leval bits
    SciaRegs.SCIFFCT.all=0x00;

    SciaRegs.SCICTL1.bit.SWRESET = 1;     //  Re-eable SCI from Reset above
    SciaRegs.SCICTL1.bit.RXENA = 1;   // Enable RX SCI and send character to SCIRXEMUa nd SCIRXBUF
    SciaRegs.SCICTL1.bit.TXENA = 1;   // TX enable

    SciaRegs.SCIFFTX.bit.TXFIFOXRESET=1;  // Re-enable TX FIFO operation 
    SciaRegs.SCIFFRX.bit.RXFIFORESET=1;  // Re-enable RX FIFO operation

    SciaRegs.SCICCR.bit.LOOPBKENA = 0;   //  Disable loop back test mode
}

//////////////////////////////////////  SCIB Port  /////////////////////////////////////////////////

interrupt void scibTxFifoIsr(void)
{

    ScibRegs.SCIFFTX.bit.TXFFINTCLR=1;    //  Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;        //  Issue PIE ACK
}

interrupt void scibRxFifoIsr(void)
{
    ScibRegs.SCITXBUF = 0x42;   //  send a "B"

    ScibRegs.SCIFFRX.bit.RXFFOVRCLR=1;    //  Clear Overflow flag
    ScibRegs.SCIFFRX.bit.RXFFINTCLR=1;   //  Clear Interrupt flag

    PieCtrlRegs.PIEACK.all|=0x100;    //  Issue PIE ack
}

void scib_fifo_init()
{
    ScibRegs.SCICCR.bit.SCICHAR =7;      //  1 stop bit,  No loopback
                                      //  No parity,8 char bits,
                                      //  async mode, idle-line protocol
    ScibRegs.SCICCR.bit.LOOPBKENA = 1;   //  Enable loop back test mode

    ScibRegs.SCICTL1.all =0x0000;     // SCI software reset

    ScibRegs.SCICTL2.bit.TXINTENA = 1;  // Enable TXRDY interrupt
    ScibRegs.SCICTL2.bit.RXBKINTENA = 1;  // Enable RXRYD/BRKDT interrupt

    ScibRegs.SCIHBAUD    =0x0001;
    ScibRegs.SCILBAUD    =0x0044;

    ScibRegs.SCIFFTX.bit.SCIRST = 1;  // Resume SCI FIFO TX/RX
    ScibRegs.SCIFFTX.bit.SCIFFENA = 1;  // Enable SCI FIFO enhancement
    ScibRegs.SCIFFTX.bit.TXFFIENA = 1;  // TX FIFO interrupt based on TXFFIVL match
    ScibRegs.SCIFFTX.bit.TXFFIL = 8;  // TX FIFO interrupt level bits

    ScibRegs.SCIFFRX.bit.RXFFIENA = 1;  // RX FIFO interrupt based on RXFFIVL match
    ScibRegs.SCIFFRX.bit.RXFFIL = 8;  // RX FIFO interrupt leval bits

    ScibRegs.SCIFFCT.all=0x00;   // FIFO delay

    ScibRegs.SCICTL1.bit.SWRESET = 1;     //  Re-eable SCI from Reset above
    ScibRegs.SCICTL1.bit.RXENA = 1;   // Enable RX SCI and send character to SCIRXEMUa nd SCIRXBUF
    ScibRegs.SCICTL1.bit.TXENA = 1;   // TX enable

    ScibRegs.SCIFFTX.bit.TXFIFOXRESET=1;  // Re-enable TX FIFO operation 
    ScibRegs.SCIFFRX.bit.RXFIFORESET=1;  // Re-enable RX FIFO operation

    ScibRegs.SCICCR.bit.LOOPBKENA = 0;   //  Disable loop back test mode
}

  • 0
    TI__Guru* 87155 points

    Minhtuan Vo,

    I did not look through your code, but looking at the problem description I see that you are trying to use both SCIA and SCIB with interrupts and FIFO enhancements.  There is a headerfile example "scia_loopback_interrupts" in the latest headerfiles of F2833x devices showing the same scenario.  Please look in to the code of this example and try fixing your code.

    Thanks and regards,

    Vamsi

     

  • 0 in reply to Vamsi Gudivada
    Intellectual 300 points

    Vamsi,

    Thanks for your help.  I am actually using that example, and everything should be the same.  Except my code does not do loopback and does not send/receive continuously.  Both TX and RX interrupt of SCIA port worked very well.  The interrupt of the SCIB RX does not seem to do anything.  SCIB interrput worked if I disable the interrupt of SCIA RX/TX as below

    PieCtrlRegs.PIEIER9.bit.INTx1=0;      // PIE Group 9, INT
    PieCtrlRegs.PIEIER9.bit.INTx2=0;      // PIE Group 9, INT

    However, SCIA won't work after that.

    Would you please take a closer look at the initial state that would allow both SCIA and SCIB working together?  Thanks.

     

  • 0 in reply to Minhtuan Vo
    TI__Guru* 87155 points

    Minhtuan Vo,

    SCI configuration looks OK except for this note:  One good practice is to do all the configuration when SCI is in reset -> Enable TXENA, RXENA and Disable loopback when SCI is in reset.  This makes sure that SCI is ready for required configuration when it is out of reset.  If not, when it comes out of reset, it starts working as it is configured already and again it sees some changes in configuration and your code may not cover all the possible events that happen because of this change.

    Apart from the above modification, you configured SCI-A and SCI-B FIFO interrupt level bits to 8 both for transmitter and receiver.  Initially when the SCI is out of reset, you will get a transmit FIFO interrupt as the transmit FIFO level is 0.  But you are not transmitting any thing in the TX ISR except clearing the interrupt flag.  Even though you clear the interrupt flag, another transmit FIFO interrupt occurs as the transmit buffer level is still 0 which is less than the TX FIFO level of 8 for which TX interrupt has been configured for.  So, SCI continuously generates TX interrupt and no data is sent in your ISR.  SCI will never receive any data because you are not transmitting any thing.  In order to receive a receive FIFO interrupt, SCI needs to receive 8 data bytes as you set RX FIFO level to 8.  But SCI is not receiving any data and hence it will never trigger a receive interrupt.  Problem is not because of using 2 SCIs. 

    So, things you want to try are:

    1)  Decide whether you need a transmit interrupt on not to transmit data.  If you don't want to send data through TX ISR, disable TX interrupt.  Initially send 8 bytes of data and expect a receive interrupt and in the receive interrupt, you can either ignore the data or use the data as you want.  You can transmit 8 bytes of data again in your receive ISR if you want another receive interrupt to occur.

    2) Change your FIFO level match bits to the desired level:  If you want to get a receive interrupt for every byte, you need to set the RX FIFO level bits accordingly.

    Hope this helps.

    Let me know if you need more explanation.

    Thanks and regards,
    Vamsi

     

  • 0 in reply to Vamsi Gudivada
    Intellectual 300 points

    Vamsi,

    Thanks for helping me to figure out the TX/RX ISR issue.  I got the RX ISR to work, but I still have a little trouble to understand the TX ISR. 

    According to the SCI reference guide, Transmit FIFO will generate interrupt when the FIFO status bits (TXFFST4–0) and FIFO level bits (TXFFIL4–0 ) match (less than or equal to).

    I want to initiate the TX ISR when I have enough 8 bytes of data to fill in the SCITXBUF.  Therefore, I initialize the TXFFIL4-0 with a level of 8.  Whenever the RX ISR initiates (received 8 bytes), I will extract one byte and fill the TX FIFO.  This process will continue until the TX FIFO has 8 bytes filled, so the TX ISR will be interrupted and 8 bytes will be transmited until the FIFO is empty.

    That's what I wanted it to do, but it does not work that way on SCIB.

    I can work around that by creating my own buffer and TX whenever it got fill, but I want to use the FIFO for better efficiency.  Would you give me a recommendation on this process?  Thank you very much.

     

  • 0 in reply to Minhtuan Vo
    TI__Guru* 87155 points

    Minhtuan Vo,

    I think you misunderstood the statement about FIFO status bits.  Let me explain.

    When you set TX FIFO level bits to 8, it means that a transmit interrupt will be generated when ever the number of bytes in TX FIFO are less than or equal to 8.

    When you set RX FIFO level bits to 8, it means that a receive interrupt will be generated when ever the number of bytes in RX FIFO is greater than or equal to 8.

    Hope this clears your doubts.

    Regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Intellectual 300 points

    Vamsi,

    Thanks for clearing up my mind.  It works now.

    Best regards,

    Minhtuan

  • 0 in reply to Vamsi Gudivada
    Prodigy 250 points

    Hi Vamsi,

    I am also using the loopback interrupt example as the basis for my program. What I didn't understand was how the TX interrupt gets triggered the first time? According to your post, that first interrupt occurred as a result of SCI coming out of reset. But how do I trigger the interrupt when I have data ready to transmit and resetting the SCI is not an option?

    Thanks.

    Siraj.

  • 0 in reply to Siraj Podikunju
    TI__Guru* 87155 points

    Siraj,

    As you said you are using loopback interrupt example, I assume you are asking this question in FIFO enabled mode.  When using FIFO, if you enable TX interrupt, an interrupt will be generated as soon as you configure the SCI and release it from reset as the TX FIFO is empty. 

    If you want to trigger transmit interrupt only when the data is ready, you can enable transmit interrupt when the data is ready and disable the transmit interrupt after the data transmit is done in the ISR.

    Thanks and regards,

    Vamsi

     

                                            

     

  • 0 in reply to Vamsi Gudivada
    Intellectual 340 points

    Gentlemen,

    Might I suggest using VisSim/ECD. It completely supports SCIA, SCIB, SCIC with full hardware FIFO support with arbitrary software queue length. It abstracts FIFO length differences between Piccolo and Delfino parts. Using a simple block diagram interface, you simply check for room in TX queue before writing TX bytes, and the SCI handler automatically sends them out. Likewise, you check the input queue length to see if sufficient bytes are available. If so, they can be read immediately. Setting, clearing and disabling of the interrupt is handled automatically.

    You can download a free 2 month trial here: http://www.vissim.com/downloads/vissim_software.html

    Regards,

    Pete

  • 0 in reply to Vamsi Gudivada
    Prodigy 250 points

    Thanks, Vamsi.

    Using the interrupt enable makes sense. I presume the ISR would disable the interrupt after sending all bytes from a buffer.

    Do you know if enabling interrupts while they are already enabled affect the sending of bytes? What would happen while the ISR is sending bytes from a ring buffer and the main loop adds more bytes to the ring buffer and then enables the SCI interrupt?

    Thanks.

    Siraj.

  • 0 in reply to Siraj Podikunju
    TI__Guru* 87155 points

    Siraj,

    As long as your code identifies that more bytes are there to transmit and make sure that the newly added bytes are written to SCITXBUFF (need to make sure that TX FIFO is not overflowing), data will be transmitted out of SCI TX pin.  If you want to use TX FIFO interrupt to alert CPU that TX FIFO is capable of accommodating some more bytes, you can enable TX FIFO level interrupt and in the ISR, data (your application code has to make sure whether there is enough data or not in the ring buffer to transmit.  If there is no enough data, don't transmit) can be written in to SCITXBUF.  If you don't want to use TX FIFO interrupt to make CPU know about the FIFO status, TX FIFO status (TXFFST) bits can be polled to know whether there is some more space available in TX FIFO or not and if space is there, data from your ring buffer can be written to SCITXBUF.

    It is always suggested to enable/disable interrupts by keeping the peripheral in reset.

    Hope this helps.

    Regards,
    Vamsi

     

         

     

  • 0 in reply to Vamsi Gudivada
    Prodigy 70 points
    Hi all,
    i've tried to make what suggested above, but i can't reach anything else than a black screen in terminal. I've setted SCIBAUD to operate on 9600 (my COM port work at this baud), but i can't do anything. If i put something in terminal, no interrupt is called.
    The only available solution is to create a polling function, with a timer that at each defined timeout check if buffer RX buffer contains something?

    Thanks a lot.
    Luca