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TMS320F28335 XINTF behaviour

john5123
Intellectual 555 points


Hi,

I thought this might be an FAQ, but can't find any related information, and the question doesn't seem to be answered in the datasheets or reference guides:

 

When the external memory interface is enabled, how do the XINTF buses and control lines behave during accesses to internal memory?

Secondly, is there any need for pull-up or pull-down resistors to hold the external memory in a safe, inactive, state during this circumstance?

 

Thanks,

John

  • 0
    TI__Guru 64600 points

    john said:

    When the external memory interface is enabled, how do the XINTF buses and control lines behave during accesses to internal memory?

    The control signals would be placed in an inactive state if the CPU is accessing internal memory.  These control signals are only activated when the CPU is accessing one of the 3 zones for the XINTF.  There is a footnote in the timing diagrams of the XINTF that indicates the XA[] address bus holds the last address put on the bus during the inactive cycles.  The XD[] data bus would go into a high-impedence state.

     

    john said:

    Secondly, is there any need for pull-up or pull-down resistors to hold the external memory in a safe, inactive, state during this circumstance?

     

    I don't believe it would be necessary for the output signals like the control signals and XA[] bus.  I don't believe there are any bus keepers internal to the device for XD[].

     

  • 0 in reply to BrandonAzbell
    Prodigy 40 points

    BrandonAzbell said:

    The control signals would be placed in an inactive state if the CPU is accessing internal memory.  These control signals are only activated when the CPU is accessing one of the 3 zones for the XINTF.  There is a footnote in the timing diagrams of the XINTF that indicates the XA[] address bus holds the last address put on the bus during the inactive cycles.  The XD[] data bus would go into a high-impedence state.

    So you mean to say that the control signals would be driven to an inactive logic 1 state, as opposed to high-Z as when external DMA takes over?

     

     

     

  • 0 in reply to Brent
    TI__Guru 64600 points

    Yes, that is correct.