If using the SM320F28335-EP with its xintf bus is it always true that an initiated read or write transaction completes its full cycle in one step once it started (chip select, read or write strobes with address or data) regardless of interrupts etc? Is it possible that part of a read or write cycle start with chip select=active, read or write=active and then ends with chip select inactive without performing the complete cycle?
Is the chip select always equal to or larger than one clk period (xclkout) for the inactive part (between consecutive reads, writes)?
Detailed comments please
