- Ask a related questionWhat is a related question?A related question is a question created from another question. When the related question is created, it will be automatically linked to the original question.
I am trying to characterize the worst case timing between a zone chip-select active low and address valid on an XINTF read cycle. Should also apply to write cycles.
Table 6-38 in the SM320F28335-EP datasheet specifies a max 1ns zone chip-select active low from the rising edge of XCLKOUT and a max 1.5ns address valid delay from the rising edge of XCLKOUT.
There is no min, so I assume 0ns min for each. I would not assume that, for instance, if the zone chip-select were to switch with a 500ps delay that the address would take 1.5ns to switch, etc. Or that the chip-select would take 1ns and address would be 0ns, etc. Silicon tends to track, so I'm wondering if this relationship is closer than Table 6-38 might appear when only looking at it relative to XCLKOUT.
What is the true worst-case timing delta between these two signals? Especially interested in the worst-case delay of address valid after chip-select low.
I understand that board fanout, loading, etc affect overall in-system timing. Just interested in the timing of the part itself in this discussion.
Thanks!
