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TMS320F28234: CPU hang when reading XINTF Zone 7

Luke Chen
Expert 5090 points
Part Number: TMS320F28234


Hi champs,

There is a bug of my customer's software, one uninitialized pointer sometimes read data from XINTF Zone 7(for example, address 0x0021059F) and this will cause CPU to hang.

My customer has more experiments, when system bootup, CPU can read XINTF Zone 6 without problem and will get hang when reading XINTF Zone 7, he enables watchdog in software so F28234 will do WD reset over and over again when this problem occurs.

According to Errata, the XINTF module may not get reset properly upon power up and this will cause CPU to hang when DSP access XINTF, I am wondering whether or not my customer's problem is identical to this one in Errata?

If watchdog is enabled and when the problem in Errata happens, DSP will do WD reset. My question is that since CPU get hang before doing WD reset, will CPU get hang again when access XINTF after WD reset or CPU will works without problems?

Please advise your comments if you have suggestions to my customer's problem, thanks for help.

Regards,

Luke

  • 0
    TI__Guru 62975 points

    Luke,

    It would be reasonable to assume that problems matching the fail description in an advisory are related to the advisory.  Please ask the customer to implement the workaround to see if the problem remains.

    In the case of improper resets, the exact fail behavior is often variable and unpredictable.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5090 points

    Tommy,

    Do you mean when that problem occurs(CPU hang), this problem could still exist even we do a watchdog reset?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke,

    If the workaround from the advisory is not implemented, there is the potential for the system to hang when accessing XINTF memory space because the module is not properly reset.  As documented in the advisory, a WD reset will perform a proper reset of XINTF, which is expected to eliminate the potential for a system hang.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5090 points

    Tommy,

    I know the workaround in Errata, let me describe my question more detailed. If we implement the workaround and we will do a watchdog reset before this problem occurs, I know this.

    My question is that if we enable watchdog and don't use the workaround, when this problem happens and cause CPU to hang, watchdog timer overflow will issue a watchdog reset, and then what will happen?

    I mean if we don't implement the workaround, this CPU hang problem will happen only once since we have watchdog reset(if enabled), is this correct? Or when this problem occurs, the problem is still there even we have the watchdog reset? I ask this because in my customer's use case, CPU hang when reading XINTF Zone 7 and watchdog reset happens over and over again, even we pull XRS pin to low for a while, the problem is still exist.

    Please advise your comments to this situation, thanks.

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke Chen said:
    My question is that if we enable watchdog and don't use the workaround, when this problem happens and cause CPU to hang, watchdog timer overflow will issue a watchdog reset, and then what will happen?

    There is no functional difference between a WD reset that is intentionally asserted vs a WD reset that is asserted due to a CPU hang timeout.

    Luke Chen said:
    I mean if we don't implement the workaround, this CPU hang problem will happen only once since we have watchdog reset(if enabled), is this correct?

    Yes.

    Luke Chen said:
    Or when this problem occurs, the problem is still there even we have the watchdog reset?

    No

    Luke Chen said:
    I ask this because in my customer's use case, CPU hang when reading XINTF Zone 7 and watchdog reset happens over and over again, even we pull XRS pin to low for a while, the problem is still exist.

    A repeated hang after WD reset would not match the advisory fail description. Check to see if XREADY is sampled for Zone 7. I am not aware of any other blocking mechanisms.

  • 0 in reply to tlee
    TI__Expert 5090 points

    Hi tlee,

    I will check this next week. Because of repeated hang problem, my customer did more experiments and he captured below power sequence figures.

    • CH1: External oscillator output(to XCLKIN)
    • CH2: The current of 5V input(before 3.3V regulator)
    • CH3: GPIO-18 for function test.
    • CH4: +3.3V

    1. Oscillator output waveform type 1

    2. Oscillator output waveform type 2

    My customer gets two different oscillator output waveforms(the red circles of above figures), he would like to know is there any side effect of the different waves above(CPU cannot boot up well)?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke,

    The oscillator glitch is not ideal because it is occurring before the 3.3V supply is powered up, but it is short enough in duration, and close enough in time to the 3.3V ramp that I would not expect it to cause a problem.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5090 points

    Hi Tommy,

    We can fix that repeated hang problem by setting USEREADY = 0, thanks for help.

    I have another question, what is the contents of M0 Vector(0x000000 - 0x00003F)? Are the values of M0 Vector fixed data?

    According to my customer, the data in M0 Vector sometimes different when DSP hang, seems that the M0 Vector contents maybe change every time system boot-up, is this correct?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke,

    That region of memory is usually allocated as general purpose SRAM for application use.  It would be up to the customer's configuration.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5090 points

    Tommy,

    According to Figure 1-80. Reset Flow Diagram in F28234 TRM, usually we use recommended flow for 280x applications and M0 vector is used for test purposes only.

    Since F28234 doesn't initialize SRAM(clear to zero), so the contents of M0 vector is unpredictable and maybe different every time when system reset, is this correct?

    The contents of M0 vector is nothing about the power sequence(rise time of 1.9V and 3.3V), is this correct?

    Please advise, thanks for help.

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke,

    Correct, the contents are not initialized by hardware.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5090 points

    Tommy,

    In errata, we provide a watchdog reset workaround to solve the CPU hang problem when accessing XINTF.

    How can we sure that this workaround fix this problem? Do we have any analysis report to prove this?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke,

    The workaround was validated once the root cause logic was identified. The Memory: Possible Incorrect Operation of XINTF Module After Power Up Advisory is the report. There is no additional documentation to share.

    -Tommy

  • 0 in reply to tlee
    TI__Expert 5090 points

    Tommy,

    I know that, but my customer wants to know how can we sure this problem is fixed after issuing a watchdog reset?

    -Luke

  • 0 in reply to Luke Chen
    TI__Guru 62975 points

    Luke,

    The Errata is considered to be an extension of the official datasheet so the recommendations in the document carry the same weight as if it were in the datasheet itself.  Also consider that this workaround has been in place for almost ten years now with no further reports of problems when the WD reset is properly applied.  And also consider that we have nothing available to share.

    -Tommy