SPI INT and OVERRUN FLAG not cleared when running from FLASH

Hi all,

I encountered a problem which is unreasonable for me, and I hope anybody probably know this can give me a hint. In short, using flash .cmd file causes the SPIFIFO INT FLAG I set failed to be cleared(which woks fine if using RAM .cmd) that future SPIFIFO interrupt is disabled. Below is the details:

I am using 28033 as my processor. And the main source file contains three parts: CPU timer interrupt ISR, SPIFIFO interrupt ISR, and infinite for loop in main function. CPU timer interrupt will be triggered at certain time interval, and this CPU timer interrupt is used to start data transmission using SPI. Then CPU timer interrupt ends and wait for the SPIFIFO interrupt. After a while when SPI data transmission complete(I set the depth of SPIFIRO RX to be 1), SPIFIFO interrupt will be triggered and do some calculation. SPIFIFO interrupt will always ends on time to get CPU ready to receive next CPU timer interrupt. In my previous program, the .cmd file is RAM type, and it works fine. After I change my .cmd file to flash which comes from ControlSuite flash .cmd file example without any modification, I made some change in my program. That is to initialize Flash registers:

InitFlash();

and this function is

void InitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;

// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.

//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3;

//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 3;

//Set the Waitstate for the OTP
FlashRegs.FOTPWAIT.bit.OTPWAIT = 5;

// CAUTION
//ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;

//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.

asm(" RPT #7 || NOP");
}

The problem for me now is that after the first time that my SPIFIFO interrupt was triggered, the INT FLAG and OVERRUN bit were both set high and not cleared ever since. However I had cleared those two bits in my SPIFIFO interrupt and it's working alright if running from RAM like the code below:

interrupt void spiRxFifoIsr(void)
{

Readvalue=(SpiaRegs.SPIRXBUF)<<2; // Read data
SpiaRegs.SPIFFRX.bit.RXFFOVFCLR=1; // Clear Overflow flag
SpiaRegs.SPIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag

}

Therefore my question is how this could be caused and could it be relevant to the Flash register setting?

Any help is appreciated!

Hezi