HRPwm of Piccolo F28069

Hello,

For a full bridge converter example with sample code, please see Section 3.3.9 of the Technical Reference Manual found at www.ti.com/lit/ug/spruh18f/spruh18f.pdf. Section 4.3 in the same document has descriptions of the HRPWM registers.

Elizabeth

Hi Hirishi,

thanks for your answer! But did you really try this? Because this is exactly what I did. But as soon as I set CTLMODE to duty control (CMPAHR) the value in  TBPHSHR is ignored and the phase shift is only generated by the value in the TBPHS without high resolution.

Kind regards - Berlin

Hi Berlin,

Yes I have done this in the past. You can have hi-res phase shift, hi-res duty and hi-res frequency all at the same time. However, to achieve this you will need to add some more software resulting in software overhead every time you change the frequency and/or the phase shift. This gets a bit difficult to manage with higher switching frequencies. 

What is the highest switching frequency you are working with?

As a side note we are planning on releasing an example to show how to achieve this on our newer devices (F2837x, F2807x). This should be available in a few months.

Hrishi

Hi!

I am having the same problem.

I can control both HR period and duty, but the hrphase is ignored, it only takes the value of the TBPHS register.

The frequency that I am using is 1MHz.

Any solution to this thread?

Thanks!

Hi Gabriel,

Can you share your configuration of the relevant registers?
Specifically, is HRPCTL[TBPSHRLOADE] and TBCTL[PHSEN] set to 1? Is MEP control selected on both edges - HRCNFG[EDGMODE] = 3?

Thanks,
Elizabeth

Hi Elizabeth,

This is the config function

void HRPWM_Config(period){
Uint16 j;
// Disable TBCLKSYNC
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
EDIS;
for (j=1;j<PWM_CH;j++){
//Write To CMP, TBPRD, TBPHS registers.
(*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW; // set Shadow load
(*ePWM[j]).TBPRD = period; // PWM frequency = 1/(2*TBPRD)
(*ePWM[j]).CMPA.half.CMPA = period / 2; // set duty 50% initially
(*ePWM[j]).CMPA.half.CMPAHR = (0 << 8); // initialize HRPWM extension
(*ePWM[j]).TBPHS.all = 0;

//Configure modes, clock dividers and action qualifier
(*ePWM[j]).TBCTR = 0;
(*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Select up-down count mode
(*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
(*ePWM[j]).TBCTL.bit.FREE_SOFT = 0;

(*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // LOAD CMPA on CTR = 0
(*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
(*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

switch (j){
case 1:
(*ePWM[j]).AQCTLA.bit.CAU = AQ_CLEAR; //GaN
(*ePWM[j]).AQCTLA.bit.CAD = AQ_SET;
break;
case 2:
(*ePWM[j]).AQCTLA.bit.CAU = AQ_CLEAR; //PMOS Low Side
(*ePWM[j]).AQCTLA.bit.CAD = AQ_SET;
break;
case 3:
(*ePWM[j]).AQCTLA.bit.CAU = AQ_CLEAR; //NMOS Low Side
(*ePWM[j]).AQCTLA.bit.CAD = AQ_SET;
break;
default:
(*ePWM[j]).AQCTLA.bit.CAU = AQ_SET; // PWM toggle high/low
(*ePWM[j]).AQCTLA.bit.CAD = AQ_CLEAR;
}
//Configure HRPWM registers
EALLOW;
(*ePWM[j]).HRCNFG.all = 0x0;
(*ePWM[j]).HRCNFG.bit.EDGMODE = HR_BEP; // MEP control on both edges
(*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP; // CMPAHR and TBPRDHR HR control
(*ePWM[j]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO_PRD; // load on CTR = 0 and CTR = TBPRD
(*ePWM[j]).HRCNFG.bit.AUTOCONV = 1; // Enable autoconversion
(*ePWM[j]).HRPCTL.bit.HRPE = 1; // Turn on high-resolution period control
if (j == 1){
(*ePWM[j]).TBCTL.bit.PHSEN = TB_DISABLE; // no sync and make this PWM master (0x0)
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // send sync pulse down-stream (0x1)
(*ePWM[j]).ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
(*ePWM[j]).ETSEL.bit.INTEN = PWM1_INT_ENABLE; // Enable INT
(*ePWM[j]).ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
}
else{
(*ePWM[j]).TBCTL.bit.PHSEN = TB_ENABLE; // sync enabled (0x1)
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; //sync to master (0x0)
(*ePWM[j]).TBCTL.bit.PHSDIR = TB_UP;
(*ePWM[j]).TBPHS.half.TBPHS = 2;
}
(*ePWM[j]).HRPCTL.bit.TBPHSHRLOADE = 1;
//Enable TBCLKSYNC
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
//Perform a software sync
EPwm1Regs.TBCTL.bit.SWFSYNC = 1;
EDIS;
}
}

Hope you can help me.
Thanks!
Gabriel

Hi Gabriel,

The configuration looks good to me. You should be able to write to TBPHS.half.TBPHSHR. Please note the lower 8 bits of this register are reserved. The TRM has more details on this.

From the Registers window, you can check the value of the TBPHSHR and compare with the value you set in the code to make sure that that they are consistent.

Elizabeth