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TMS320F28075PTP VREGENZ pin and 1.2V question for programming

Andrew La Pietra
Prodigy 60 points

We are seeing a droop on VDD during bootloading over JTAG causing bootload to fail.   Did not see this on TMX version of PCB (Custom Motor Control Bd. )

VDD is drooping by 200mV we are also seeing REVERSE current flow into external 1.2V regulator.  About 2.4msec duration.  VREGENZ is pulled directly to VDDIO (3.3V).  When pin is lifted 28075 programs fine. 

Why would uP supply VDD (1.2V) current back into regulator when the internal regulator is disabled?

Thanks,

Andy

  • 0
    TI__Expert 7885 points
    Hi Andrew,

    Do you have a scope shot you can share? On your board for normal operation, are you using internal VREG or an external supply for 1.2V VDD rail? Which revision of silicon are you using?

    The revision can be found on the top of the device. It is the third letter of the third line of text. See p. 5 and of www.ti.com/.../sprz423c.pdf

    If revB, the behavior is likely due to the usage note on p. 12 of the above linked document.

    Best Regards,
    Adam Dunhoft
  • 0 in reply to Adam Dunhoft
    Prodigy 60 points
    Adam,

    We have a 1.2V external regulator (MAX15102) attached. I don't have a screen shot right now but the droop is 2.4mS long and dips 200mV to about 1.0 volts. Shaped as a rounded V...

    I saw the Errata sheet on the silicon. Our prototype used TMX part...this version is TMS. Don't believe we have B rev. silicon. We only saw this problem during bootloading via TJAG, not flash programming (via CAN).

    Oddly enough, when we cut the VDDIO (3.3V) trace to VREGENZ the board programmed without issue.
  • 0 in reply to Andrew La Pietra
    TI__Expert 7885 points
    Andrew,

    Just to clarify "during bootloading via JTAG" does this glitch happen during CCS connect, JTAG RAM pattern load or when you run the RAM pattern?

    It sounds like your LDO is unable to react quick enough to the current load. Do you have the 22uF cap on the output of your MAX15102 shown in the datasheet? If not, what value of total cap do you have on the VDD rail?

    1. Do you have a schematic you can share? You can send it to my email if you don't want it posted on the forum.
    2. Would it be possible to get the waveforms from the scope of the glitch?
    3. Would it be possible to get the VDDIO, VDD, iVDD and XRSn waveforms during power-up?

    Best Regards,
    Adam Dunhoft